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Searched refs:PLL (Results 1 – 25 of 118) sorted by relevance

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/freebsd/sys/arm64/qoriq/clk/
H A Dlx2160a_clkgen.c49 #define PLL(_id1, _id2, cname, o, d) \ macro
67 PLL(QORIQ_TYPE_PLATFORM_PLL, 0, "platform_pll", 0x60080, plt_divs);
69 PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cga_divs);
71 PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cga_divs);
73 PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cgb_divs);
75 PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cgb_divs);
87 {PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cg_divs)},
89 {PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cg_divs)},
91 {PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cg_divs)},
93 {PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cg_divs)},
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dbrcm,iproc-clocks.txt8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
22 clock control registers required for the PLL
25 The input parent clock phandle for the PLL. For most iProc PLLs, this is an
89 PLL and leaf clock compatible strings for Cygnus are:
97 The following table defines the set of PLL/clock index and ID for Cygnus.
142 PLL and leaf clock compatible strings for Hurricane 2 are:
145 The following table defines the set of PLL/clock for Hurricane 2:
156 PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
[all …]
H A Dxgene.txt9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
21 - clock-output-names : shall be the name of the PLL referenced by derive
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
32 Optional properties for PLL clocks:
H A Ddove-divider-clock.txt1 PLL divider based Dove clocks
3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
H A Dti,cdce925.txt16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
48 /* PLL options to get SSC 1% centered */
H A Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
H A Daxs10x-i2s-pll-clock.txt1 Binding for the AXS10X I2S PLL clock
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
H A Dsnps,pll-clock.txt1 Binding for the AXS10X Generic PLL clock
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
H A Dqoriq-clock.txt5 multiple phase locked loops (PLL) to create a variety of frequencies
70 platform PLL.
117 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
118 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
125 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
126 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
132 * 0 - equal to the PLL frequency
133 * 1 - equal to the PLL frequency divided by 2
134 * 2 - equal to the PLL frequency divided by 4
H A Dkeystone-pll.txt3 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
6 PLL is controlled by a PLL controller registers along with memory mapped
H A Dsilabs,si5341.txt13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
52 - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
53 feedback divider. Must be such that the PLL output is in the valid range. For
56 If these are not specified, and the PLL is not yet programmed when the driver
57 probes, the PLL will be set to 14GHz.
117 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
H A Dclk-s5pv210-audss.txt15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
16 not specified (i.e. xusbxti is used for PLL reference), it is fixed to
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
H A Dbrcm,bcm2835-cprman.txt8 oscillator, a level of PLL dividers that produce channels off of the
10 the PLL channels. Most other hardware components source from the
12 the PLL dividers directly.
H A Dsnps,hsdk-pll-clock.txt1 Binding for the HSDK Generic PLL clock
13 - clocks: shall be the input parent clock phandle for the PLL.
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/davinci/
H A Dpll.txt1 Binding for TI DaVinci PLL Controllers
3 The PLL provides clocks to most of the components on the SoC. In addition
4 to the PLL itself, this controller also contains bypasses, gates, dividers,
26 Describes the main PLL clock output (before POSTDIV). The node name must
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dtas2552.txt19 internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
22 defined values to select and configure the PLL and PDM reference clocks.
H A Dbrcm,cygnus-audio.txt12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
15 (usually the PLL)
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-stm32-usbphyc.txt6 PLL configuration.
9 |_ PLL
25 - clocks: phandle + clock specifier for the PLL phy clock
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
/freebsd/sys/riscv/sifive/
H A Dsifive_prci.c111 #define PLL(_id, _name, _base) \ macro
118 #define PLL_END PLL(0, NULL, 0)
177 PLL(FU540_PRCI_CORECLK, "coreclk", FU540_PRCI_COREPLL_CFG0),
178 PLL(FU540_PRCI_DDRCLK, "ddrclk", FU540_PRCI_DDRPLL_CFG0),
179 PLL(FU540_PRCI_GEMGXLCLK, "gemgxlclk", FU540_PRCI_GEMGXLPLL_CFG0),
224 PLL(FU740_PRCI_CORECLK, "coreclk", FU740_PRCI_COREPLL_CFG0),
225 PLL(FU740_PRCI_DDRCLK, "ddrclk", FU740_PRCI_DDRPLL_CFG0),
226 PLL(FU740_PRCI_GEMGXLCLK, "gemgxlclk", FU740_PRCI_GEMGXLPLL_CFG0),
227 PLL(FU740_PRCI_DVFSCORECLK, "dvfscoreclk", FU740_PRCI_DVFSCOREPLL_CFG0),
228 PLL(FU740_PRCI_HFPCLK, "hfpclk", FU740_PRCI_HFPCLKPLL_CFG0),
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dnvidia,tegra124-cpufreq.txt12 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL rate changes.
/freebsd/sys/contrib/device-tree/Bindings/c6x/
H A Dclocks.txt1 C6X PLL Clock Controllers
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c116 #define PLL(_id, cname, pname) \ macro
218 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
229 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
242 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
255 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
266 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
277 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
290 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
300 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
310 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dadv7343.txt14 micro ampere level. All DACs and the internal PLL
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
17 internal PLL 1 circuit to be powered down and the
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c144 #define PLL(_id, cname, pname) \ macro
272 PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"),
284 PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"),
296 PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"),
308 PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
319 PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
330 PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
341 PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"),
358 PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
370 PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"),
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dnvidia,tegra124-xusb.txt49 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
50 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
51 - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
59 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
60 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
61 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.

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