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Searched refs:PFALSE (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h82 PFALSE, enumerator
H A DHexagonISelLowering.cpp1967 case HexagonISD::PFALSE: return "HexagonISD::PFALSE"; in getTargetNodeName()
2993 return DAG.getNode(HexagonISD::PFALSE, dl, VecTy); in LowerBUILD_VECTOR()
3527 case HexagonISD::PFALSE: in PerformDAGCombine()
H A DHexagonPatterns.td97 def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA510.td611 def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
H A DAArch64SchedA320.td633 def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
H A DAArch64SchedNeoverseV1.td1464 "^PFALSE$", "^PFIRST_B$",
H A DAArch64SchedA64FX.td2094 "^NANDS?_P", "^NORS?_P", "^ORNS?_P", "^PFALSE", "^PNEXT",
H A DAArch64SchedNeoverseN2.td1597 def : InstRW<[N2Write_2c_1M], (instregex "^PFALSE$", "^PTRUE_[BHSD]$")>;
H A DAArch64SchedNeoverseN3.td1567 def : InstRW<[N3Write_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
H A DAArch64FrameLowering.cpp1068 BuildMI(MBB, MBBI, DL, TII.get(AArch64::PFALSE), PReg); in emitZeroCallUsedRegs()
H A DAArch64SchedNeoverseV2.td2082 def : InstRW<[V2Write_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
H A DAArch64SVEInstrInfo.td1073 defm PFALSE : sve_int_pfalse<0b000000, "pfalse">;
4385 def : InstAlias<"pfalse\t$Pd", (PFALSE PPRorPNR8:$Pd), 0>;