Home
last modified time | relevance | path

Searched refs:PFALSE (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h82 PFALSE, enumerator
H A DHexagonISelLowering.cpp1945 case HexagonISD::PFALSE: return "HexagonISD::PFALSE"; in getTargetNodeName()
2971 return DAG.getNode(HexagonISD::PFALSE, dl, VecTy); in LowerBUILD_VECTOR()
3505 case HexagonISD::PFALSE: in PerformDAGCombine()
H A DHexagonPatterns.td97 def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA510.td611 def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
H A DAArch64SchedNeoverseV1.td1351 "^PFALSE$", "^PFIRST_B$",
H A DAArch64SchedA64FX.td2094 "^NANDS?_P", "^NORS?_P", "^ORNS?_P", "^PFALSE", "^PNEXT",
H A DAArch64SchedNeoverseN2.td1556 def : InstRW<[N2Write_2cyc_1M], (instregex "^PFALSE$", "^PTRUE_[BHSD]$")>;
H A DAArch64FrameLowering.cpp1037 BuildMI(MBB, MBBI, DL, TII.get(AArch64::PFALSE), PReg); in emitZeroCallUsedRegs()
H A DAArch64SchedNeoverseV2.td2065 def : InstRW<[V2Write_2cyc_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
H A DAArch64SVEInstrInfo.td952 defm PFALSE : sve_int_pfalse<0b000000, "pfalse">;
4108 def : InstAlias<"pfalse\t$Pd", (PFALSE PPRorPNR8:$Pd), 0>;