Searched refs:P5600 (Results 1 – 4 of 4) sorted by relevance
238 "MipsSubtarget::CPU::P5600",239 "The P5600 Processor", [FeatureMips32r5]>;
47 enum class CPU { P5600 }; enumerator
1 //==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===//597 // The following instruction classes are never valid on P5600.603 // The following instructions are never valid on P5600.
29363 1028 2060 NVMe SED MU U.2 1.6TB (P5600)29364 1028 2061 NVMe SED MU U.2 3.2TB (P5600)29365 1028 2062 NVMe SED MU U.2 6.4TB (P5600)29369 1028 209e NVMe MU U.2 1.6TB (P5600)29370 1028 209f NVMe MU U.2 3.2TB (P5600)29371 1028 2100 NVMe MU U.2 6.4TB (P5600)