Searched refs:P5600 (Results 1 – 4 of 4) sorted by relevance
239 "MipsSubtarget::CPU::P5600",240 "The P5600 Processor", [FeatureMips32r5]>;
46 enum class CPU { Others, P5600, I6400, I6500 }; enumerator
1 //==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===//597 // The following instruction classes are never valid on P5600.603 // The following instructions are never valid on P5600.
31179 1028 2060 NVMe SED MU U.2 1.6TB (P5600)31180 1028 2061 NVMe SED MU U.2 3.2TB (P5600)31181 1028 2062 NVMe SED MU U.2 6.4TB (P5600)31185 1028 209e NVMe MU U.2 1.6TB (P5600)31186 1028 209f NVMe MU U.2 3.2TB (P5600)31187 1028 2100 NVMe MU U.2 6.4TB (P5600)