| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCCState.h | 52 void PreAnalyzeCallReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs, const Type *RetTy);
57 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
74 PreAnalyzeReturnForVectorFloat(const SmallVectorImpl<ISD::OutputArg> &Outs);
104 const SmallVectorImpl<ISD::OutputArg> &Outs, CCAssignFn Fn, in PreAnalyzeCallOperands() argument
110 PreAnalyzeCallOperands(Outs, FuncArgs, Func); in PreAnalyzeCallOperands()
114 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
118 PreAnalyzeCallOperands(Outs, Fn, FuncArgs, Func); in AnalyzeCallOperands()
119 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
125 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
127 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
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| H A D | MipsCCState.cpp | 98 const SmallVectorImpl<ISD::OutputArg> &Outs, const Type *RetTy) { in PreAnalyzeCallReturnForF128() argument
99 for (unsigned i = 0; i < Outs.size(); ++i) { in PreAnalyzeCallReturnForF128()
119 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForVectorFloat() argument
120 for (unsigned i = 0; i < Outs.size(); ++i) { in PreAnalyzeReturnForVectorFloat()
121 ISD::OutputArg Out = Outs[i]; in PreAnalyzeReturnForVectorFloat()
142 const SmallVectorImpl<ISD::OutputArg> &Outs, in PreAnalyzeCallOperands() argument
145 for (unsigned i = 0; i < Outs.size(); ++i) { in PreAnalyzeCallOperands()
146 TargetLowering::ArgListEntry FuncArg = FuncArgs[Outs[i].OrigArgIndex]; in PreAnalyzeCallOperands()
151 CallOperandIsFixed.push_back(Outs[i].IsFixed); in PreAnalyzeCallOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCCState.h | 23 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
57 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
60 IsFixed.resize(Outs.size(), false); in AnalyzeCallOperands()
61 for (unsigned ValNo = 0, E = Outs.size(); ValNo != E; ++ValNo) in AnalyzeCallOperands()
62 if (Outs[ValNo].IsFixed) in AnalyzeCallOperands()
65 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
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| H A D | PPCCCState.cpp | 15 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeCallOperands() argument
16 for (const auto &I : Outs) { in PreAnalyzeCallOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 99 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn() argument
102 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in CheckReturn()
103 MVT VT = Outs[i].VT; in CheckReturn()
104 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in CheckReturn()
113 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn() argument
116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in AnalyzeReturn()
117 MVT VT = Outs[i].VT; in AnalyzeReturn()
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in AnalyzeReturn()
126 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
128 unsigned NumOps = Outs.size(); in AnalyzeCallOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCallingConv.h | 65 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
69 for (unsigned i = 0; i < Outs.size(); ++i) in AnalyzeCallOperands()
70 ArgIsFixed.push_back(Outs[i].IsFixed); in AnalyzeCallOperands()
73 for (unsigned i = 0; i < Outs.size(); ++i) in AnalyzeCallOperands()
74 ArgIsShortVector.push_back(IsShortVectorType(Outs[i].ArgVT)); in AnalyzeCallOperands()
76 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
81 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.h | 112 const SmallVectorImpl<ISD::OutputArg> &Outs,
116 const SmallVectorImpl<ISD::OutputArg> &Outs,
121 const SmallVectorImpl<ISD::OutputArg> &Outs,
126 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.h | 50 const SmallVectorImpl<ISD::OutputArg> &Outs,
76 const SmallVectorImpl<ISD::OutputArg> &Outs,
104 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| H A D | LanaiISelLowering.cpp | 401 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
416 return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs, in LowerCall()
522 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context, in CanLowerReturn() argument
527 return CCInfo.CheckReturn(Outs, RetCC_Lanai32); in CanLowerReturn()
533 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
544 CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32); in LowerReturn()
595 bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo() argument
613 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg); in LowerCCCCallTo()
616 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast); in LowerCCCCallTo()
618 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32); in LowerCCCCallTo()
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| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | InitLLVM.cpp | 36 llvm::raw_ostream *Outs = &llvm::outs(), *Errs = &llvm::errs(); in CleanupStdHandles() local
37 Outs->flush(); in CleanupStdHandles()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 89 const SmallVectorImpl<ISD::OutputArg> &Outs,
119 const SmallVectorImpl<ISD::OutputArg> &Outs,
123 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| H A D | MSP430ISelLowering.cpp | 321 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeVarArgs() argument
322 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack); in AnalyzeVarArgs()
435 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeRetResult() argument
436 State.AnalyzeReturn(Outs, RetCC_MSP430); in AnalyzeRetResult()
469 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
488 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
606 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn() argument
611 return CCInfo.CheckReturn(Outs, RetCC_MSP430); in CanLowerReturn()
617 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
627 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 275 LLVM_ABI void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
281 LLVM_ABI bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
286 LLVM_ABI void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
296 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeArguments() argument
298 AnalyzeCallOperands(Outs, Fn); in AnalyzeArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.h | 204 const SmallVectorImpl<ISD::OutputArg> &Outs,
210 const SmallVectorImpl<ISD::OutputArg> &Outs,
251 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 680 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context, in CanLowerReturn() argument
684 return CCInfo.CheckReturn(Outs, RetCC_X86); in CanLowerReturn()
755 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
768 if (CallConv == CallingConv::X86_INTR && !Outs.empty()) in LowerReturn()
773 CCInfo.AnalyzeReturn(Outs, RetCC_X86); in LowerReturn()
2027 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
2043 bool IsCalleePopSRet = !IsGuaranteeTCO && hasCalleePopSRet(Outs, Subtarget); in LowerCall()
2077 CCInfo.AnalyzeArguments(Outs, CC_X86); in LowerCall()
2082 CCInfo.AnalyzeArgumentsSecondPass(Outs, CC_X86); in LowerCall()
2149 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) { in LowerCall()
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| H A D | X86CallLowering.h | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.h | 140 const SmallVectorImpl<ISD::OutputArg> &Outs,
144 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 114 const SmallVectorImpl<ISD::OutputArg> &Outs,
118 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 250 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
265 CCInfo.AnalyzeCallOperands(Outs, CC_ARC); in LowerCall()
616 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context, in CanLowerReturn() argument
620 if (!CCInfo.CheckReturn(Outs, RetCC_ARC)) in CanLowerReturn()
630 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
648 CCInfo.AnalyzeReturn(Outs, RetCC_ARC); in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.h | 88 const SmallVectorImpl<ISD::OutputArg> &Outs,
150 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.h | 36 SmallVectorImpl<BaseArgInfo> &Outs,
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/ |
| H A D | PatternParser.cpp | 339 const DagInit *Outs = Def->getValueAsDag("OutOperands"); in parsePatFragImpl() local
340 if (Outs->getOperatorAsDef(Def->getLoc())->getName() != "outs") { in parsePatFragImpl()
347 if (!parsePatFragParamList(*Outs, [&](StringRef Name, unsigned Kind) { in parsePatFragImpl()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 491 bool checkReturn(CCState &CCInfo, SmallVectorImpl<BaseArgInfo> &Outs,
497 SmallVectorImpl<BaseArgInfo> &Outs,
509 SmallVectorImpl<BaseArgInfo> &Outs, in canLowerReturn() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.h | 91 const SmallVectorImpl<ISD::OutputArg> &Outs,
95 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.h | 46 const SmallVectorImpl<ISD::OutputArg> &Outs,
50 const SmallVectorImpl<ISD::OutputArg> &Outs,
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