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Searched refs:Outputs (Results 1 – 25 of 32) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp187 CellMapType &Outputs) const { in evaluate()
213 return evaluateLoad(MI, Inputs, Outputs); in evaluate()
232 if (evaluateFormalCopy(MI, Inputs, Outputs)) in evaluate()
258 auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs) in evaluate()
260 putCell(Reg[0], Val, Outputs); in evaluate()
323 return rr0(eIMM(im(1), W0), Outputs); in evaluate()
325 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); in evaluate()
327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); in evaluate()
335 return rr0(RC, Outputs); in evaluate()
343 return rr0(rc(1), Outputs); in evaluate()
[all …]
H A DHexagonConstPropagation.cpp301 // compute the set of output values "Outputs". An example of when
314 CellMap &Outputs) = 0;
687 CellMap Outputs; in visitNonBranch() local
688 bool Eval = MCE.evaluate(MI, Cells, Outputs); in visitNonBranch()
692 for (auto &I : Outputs) in visitNonBranch()
716 if (!Outputs.has(DefR.Reg)) in visitNonBranch()
719 Changed = RC.meet(Outputs.get(DefR.Reg)); in visitNonBranch()
1845 CellMap &Outputs) override;
1864 CellMap &Outputs);
1869 CellMap &Outputs);
1925 evaluate(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluate() argument
2553 evaluateHexCompare(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexCompare() argument
2628 evaluateHexLogical(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexLogical() argument
2675 evaluateHexCondMove(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexCondMove() argument
2718 evaluateHexExt(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexExt() argument
2762 evaluateHexVector1(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexVector1() argument
[all...]
H A DHexagonBitTracker.h35 CellMapType &Outputs) const override;
53 CellMapType &Outputs) const;
55 CellMapType &Outputs) const;
H A DBitTracker.cpp721 CellMapType &Outputs) const { in evaluate()
737 putCell(RD, Res, Outputs); in evaluate()
754 putCell(RD, Res, Outputs); in evaluate()
H A DBitTracker.h472 CellMapType &Outputs) const;
/freebsd/crypto/openssl/doc/man1/
H A Dopenssl-info.pod.in40 Outputs the default directory for OpenSSL configuration files.
44 Outputs the default directory for OpenSSL engine modules.
48 Outputs the default directory for OpenSSL dynamically loadable modules
53 Outputs the DSO extension OpenSSL uses.
57 Outputs the separator character between a directory specification and
64 Outputs the OpenSSL list separator character.
70 Outputs the randomness seed sources.
74 Outputs the OpenSSL CPU settings info.
H A Dopenssl-crl.pod.in120 Outputs the "hash" of the CRL issuer name using the older algorithm
/freebsd/contrib/llvm-project/clang/lib/Driver/
H A DTool.cpp21 const InputInfoList &Outputs, in ConstructJobMultipleOutputs() argument
25 assert(Outputs.size() == 1 && "Expected only one output by default!"); in ConstructJobMultipleOutputs()
26 ConstructJob(C, JA, Outputs.front(), Inputs, TCArgs, LinkingOutput); in ConstructJobMultipleOutputs()
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dti,cdce925.txt16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
H A Dsilabs,si5341.txt74 == Child nodes: Outputs ==
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DTFLiteUtils.cpp41 EvaluationResultImpl(const std::vector<const TfLiteTensor *> &Outputs) in EvaluationResultImpl() argument
42 : Outputs(Outputs){}; in EvaluationResultImpl()
44 const TfLiteTensor *getOutput(size_t I) { return Outputs[I]; } in getOutput()
50 const std::vector<const TfLiteTensor *> Outputs; member in llvm::EvaluationResultImpl
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DCodeExtractor.h174 ValueSet &Inputs, ValueSet &Outputs);
200 void findInputsOutputs(ValueSet &Inputs, ValueSet &Outputs,
/freebsd/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DIROutliner.cpp868 SetVector<Value *> &ArgInputs, SetVector<Value *> &Outputs) { in getCodeExtractorArguments() argument
901 CE->findInputsOutputs(PremappedInputs, Outputs, SinkCands); in getCodeExtractorArguments()
1098 DenseSet<BasicBlock *> &RegionBlocks, SetVector<Value *> &Outputs, in analyzeExitPHIsForOutputUses() argument
1123 Outputs.insert(&PN); in analyzeExitPHIsForOutputUses()
1279 SetVector<Value *> &Outputs) { in findExtractedOutputToOverallOutputMapping() argument
1300 analyzeExitPHIsForOutputUses(ExitBB, Exits, BlocksInRegion, Outputs, in findExtractedOutputToOverallOutputMapping()
1318 for (Value *Output : Outputs) { in findExtractedOutputToOverallOutputMapping()
1406 SetVector<Value *> ArgInputs, Outputs; in findAddInputsOutputs() local
1409 Outputs); in findAddInputsOutputs()
1420 findExtractedOutputToOverallOutputMapping(M, Region, Outputs); in findAddInputsOutputs()
[all …]
H A DHotColdSplitting.cpp398 SetVector<Value *> Inputs, Outputs, Sinks; in isSplittingBeneficial() local
399 CE.findInputsOutputs(Inputs, Outputs, Sinks); in isSplittingBeneficial()
402 getOutliningPenalty(Region, Inputs.size(), Outputs.size()); in isSplittingBeneficial()
H A DPartialInlining.cpp1108 SetVector<Value *> Inputs, Outputs, Sinks; in doMultiRegionFunctionOutlining() local
1119 CE.findInputsOutputs(Inputs, Outputs, Sinks); in doMultiRegionFunctionOutlining()
1123 dbgs() << "outputs: " << Outputs.size() << "\n"; in doMultiRegionFunctionOutlining()
1126 for (Value *output : Outputs) in doMultiRegionFunctionOutlining()
1131 if (Outputs.size() > 0 && !ForceLiveExit) in doMultiRegionFunctionOutlining()
/freebsd/contrib/llvm-project/clang/include/clang/Driver/
H A DJob.h175 ArrayRef<InputInfo> Outputs = std::nullopt,
249 ArrayRef<InputInfo> Outputs = std::nullopt,
H A DTool.h88 const InputInfoList &Outputs,
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/IPO/
H A DIROutliner.h294 ArrayRef<Value *> Outputs, LoadInst *LI);
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dti,sci-intr.txt11 | Inputs Outputs |
H A Dbrcm,bcm7120-l2-intc.txt24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
/freebsd/share/examples/BSD_daemon/
H A DREADME64 An example of how to use the stuff above. Outputs a simple
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DClang.h156 const InputInfoList &Outputs,
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DCodeExtractor.cpp646 void CodeExtractor::findInputsOutputs(ValueSet &Inputs, ValueSet &Outputs, in findInputsOutputs() argument
660 Outputs.insert(&II); in findInputsOutputs()
1712 ValueSet Inputs, Outputs; in extractCodeRegion() local
1713 return extractCodeRegion(CEAC, Inputs, Outputs); in extractCodeRegion()
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddm814x-clocks.dtsi6 * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMIRPrinter.cpp298 std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value, in printStackObjectDbgInfo() local
305 raw_string_ostream StrOS(*Outputs[i]); in printStackObjectDbgInfo()

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