| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 41 EVT OutVT = N->getValueType(0); in ExpandRes_BITCAST() local
42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
67 TLI.hasBigEndianPartOrdering(OutVT, DL)) in ExpandRes_BITCAST()
75 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
94 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
186 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
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| H A D | LegalizeIntegerTypes.cpp | 466 EVT OutVT = N->getValueType(0); in PromoteIntRes_BITCAST() local
467 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in PromoteIntRes_BITCAST()
544 TypeSize OutSize = OutVT.getSizeInBits(); in PromoteIntRes_BITCAST()
548 EVT::getVectorVT(*DAG.getContext(), OutVT.getVectorElementType(), in PromoteIntRes_BITCAST()
549 OutVT.getVectorElementCount() * Scale); in PromoteIntRes_BITCAST()
552 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
561 CreateStackStoreLoad(InOp, OutVT)); in PromoteIntRes_BITCAST()
5704 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_SPLICE() local
5706 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2)); in PromoteIntRes_VECTOR_SPLICE()
5724 EVT OutVT = N->getValueType(0); in PromoteIntRes_EXTRACT_SUBVECTOR() local
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| H A D | LegalizeVectorTypes.cpp | 3394 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp() local
3398 Lo = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
3400 Hi = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
3417 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo, MaskLo, EVLLo); in SplitVecOp_UnaryOp()
3418 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi, MaskHi, EVLHi); in SplitVecOp_UnaryOp()
3420 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); in SplitVecOp_UnaryOp()
3421 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); in SplitVecOp_UnaryOp()
4016 EVT OutVT = N->getValueType(0); in SplitVecOp_TruncateHelper() local
4017 ElementCount NumElements = OutVT.getVectorElementCount(); in SplitVecOp_TruncateHelper()
4018 bool IsFloat = OutVT.isFloatingPoint(); in SplitVecOp_TruncateHelper()
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| H A D | SelectionDAGBuilder.cpp | 12428 EVT OutVT = in visitVectorDeinterleave() local
12431 unsigned OutNumElts = OutVT.getVectorMinNumElements(); in visitVectorDeinterleave()
12434 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
12436 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
12441 if (OutVT.isFixedLengthVector()) { in visitVectorDeinterleave()
12442 SDValue Even = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, in visitVectorDeinterleave()
12444 SDValue Odd = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, in visitVectorDeinterleave()
12452 DAG.getVTList(OutVT, OutVT), Lo, Hi); in visitVectorDeinterleave()
12462 EVT OutVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitVectorInterleave() local
12466 if (OutVT.isFixedLengthVector()) { in visitVectorInterleave()
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| H A D | DAGCombiner.cpp | 641 std::optional<EVT> OutVT = std::nullopt);
25207 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); in canCombineShuffleToExtendVectorInreg() local
25209 if ((LegalTypes && !TLI.isTypeLegal(OutVT)) || in canCombineShuffleToExtendVectorInreg()
25210 (LegalOperations && !TLI.isOperationLegalOrCustom(Opcode, OutVT))) in canCombineShuffleToExtendVectorInreg()
25214 return OutVT; in canCombineShuffleToExtendVectorInreg()
25251 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( in combineShuffleToAnyExtendVectorInreg() local
25253 if (!OutVT) in combineShuffleToAnyExtendVectorInreg()
25255 return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, N0)); in combineShuffleToAnyExtendVectorInreg()
25372 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( in combineShuffleToZeroExtendVectorInReg() local
25375 if (OutVT) in combineShuffleToZeroExtendVectorInReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2745 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
2748 OutVT = MVT::i16; in truncateVectorWithNARROW()
2752 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithNARROW()
2762 SDValue Res = DAG.getNode(WebAssemblyISD::NARROW_U, DL, OutVT, Lo, Hi); in truncateVectorWithNARROW()
2785 EVT OutVT = N->getValueType(0); in performTruncateCombine() local
2786 if (!OutVT.isVector()) in performTruncateCombine()
2789 EVT OutSVT = OutVT.getVectorElementType(); in performTruncateCombine()
2793 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector())) in performTruncateCombine()
2798 OutVT.getScalarSizeInBits()); in performTruncateCombine()
2800 return truncateVectorWithNARROW(OutVT, In, DL, DAG); in performTruncateCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5179 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8), in getPermuteNode() local
5181 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1); in getPermuteNode()
5559 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits), in insertUnpackIfPrepared() local
5561 return DAG.getNode(SystemZISD::UNPACKL_HIGH, DL, OutVT, PackedOp); in insertUnpackIfPrepared()
5964 EVT OutVT = Op.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
5966 unsigned ToBits = OutVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
5970 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits), in lowerSIGN_EXTEND_VECTOR_INREG() local
5973 DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(PackedOp), OutVT, PackedOp); in lowerSIGN_EXTEND_VECTOR_INREG()
5983 EVT OutVT = Op.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
5986 unsigned OutNumElts = OutVT.getVectorNumElements(); in lowerZERO_EXTEND_VECTOR_INREG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 2790 ValueType OutVT, ValueType InVT,
2793 …def : SVE_4_Op_Imm_Pat<OutVT, op, OutVT, InVT, InVT, i32, VectorIndexH32b_timm, !cast<Instruction>…
2826 multiclass sve2_fp_mla_long<bits<3> opc, string asm, ValueType OutVT,
2829 def : SVE_3_Op_Pat<OutVT, op, OutVT, InVT, InVT, !cast<Instruction>(NAME)>;
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| H A D | AArch64ISelLowering.cpp | 21066 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); in getPTest() local
21067 SDValue TVal = DAG.getConstant(1, DL, OutVT); in getPTest()
21068 SDValue FVal = DAG.getConstant(0, DL, OutVT); in getPTest()
21088 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test); in getPTest()
24695 SDValue OutVT = DAG.getValueType(RetVT); in performGatherLoadCombine() local
24697 OutVT = DAG.getValueType(HwRetVt); in performGatherLoadCombine()
24702 Base, Offset, OutVT}; in performGatherLoadCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrSSE.td | 3784 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3795 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3804 (OutVT (OpNode (ArgVT RC:$src1),
3809 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3820 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3829 (OutVT (OpNode (ArgVT RC:$src1),
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| H A D | X86ISelLowering.cpp | 20332 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithPACK() local
20336 OutVT = MVT::i16; in truncateVectorWithPACK()
20343 OutVT = EVT::getVectorVT(Ctx, OutVT, 128 / OutVT.getSizeInBits()); in truncateVectorWithPACK()
20347 SDValue Res = DAG.getNode(Opcode, DL, OutVT, LHS, RHS); in truncateVectorWithPACK()
20367 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithPACK()
20373 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
20382 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
20388 int Scale = 64 / OutVT.getScalarSizeInBits(); in truncateVectorWithPACK()
20390 Res = DAG.getVectorShuffle(OutVT, DL, Res, Res, Mask); in truncateVectorWithPACK()
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| H A D | X86InstrAVX512.td | 161 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
166 AVX512_maskable_common<O, F, OutVT, Outs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8784 EVT OutVT = Op.getValueType(); in LowerINT_TO_FP() local
8785 if (OutVT.isVector() && OutVT.isFloatingPoint() && in LowerINT_TO_FP()
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