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Searched refs:OutVT (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp41 EVT OutVT = N->getValueType(0); in ExpandRes_BITCAST() local
42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
67 TLI.hasBigEndianPartOrdering(OutVT, DL)) in ExpandRes_BITCAST()
75 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
94 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
186 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
H A DLegalizeIntegerTypes.cpp483 EVT OutVT = N->getValueType(0); in PromoteIntRes_BITCAST() local
484 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in PromoteIntRes_BITCAST()
561 TypeSize OutSize = OutVT.getSizeInBits(); in PromoteIntRes_BITCAST()
565 EVT::getVectorVT(*DAG.getContext(), OutVT.getVectorElementType(), in PromoteIntRes_BITCAST()
566 OutVT.getVectorElementCount() * Scale); in PromoteIntRes_BITCAST()
569 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
601 CreateStackStoreLoad(InOp, OutVT)); in PromoteIntRes_BITCAST()
2205 EVT OutVT = N->getValueType(0); in PromoteIntOp_BITCAST() local
2214 if (OutVT.isVector() && DAG.getDataLayout().isLittleEndian()) { in PromoteIntOp_BITCAST()
2215 EVT EltVT = OutVT.getVectorElementType(); in PromoteIntOp_BITCAST()
[all …]
H A DLegalizeVectorTypes.cpp3700 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp() local
3704 Lo = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
3706 Hi = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
3723 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo, MaskLo, EVLLo); in SplitVecOp_UnaryOp()
3724 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi, MaskHi, EVLHi); in SplitVecOp_UnaryOp()
3726 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); in SplitVecOp_UnaryOp()
3727 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); in SplitVecOp_UnaryOp()
4329 EVT OutVT = N->getValueType(0); in SplitVecOp_TruncateHelper() local
4330 ElementCount NumElements = OutVT.getVectorElementCount(); in SplitVecOp_TruncateHelper()
4331 bool IsFloat = OutVT.isFloatingPoint(); in SplitVecOp_TruncateHelper()
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H A DSelectionDAGBuilder.cpp12585 EVT OutVT = ValueVTs[0]; in visitVectorDeinterleave() local
12586 unsigned OutNumElts = OutVT.getVectorMinNumElements(); in visitVectorDeinterleave()
12590 assert(ValueVTs[i] == OutVT && "Expected VTs to be the same"); in visitVectorDeinterleave()
12591 SubVecs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
12597 if (OutVT.isFixedLengthVector() && Factor == 2) { in visitVectorDeinterleave()
12598 SDValue Even = DAG.getVectorShuffle(OutVT, DL, SubVecs[0], SubVecs[1], in visitVectorDeinterleave()
12600 SDValue Odd = DAG.getVectorShuffle(OutVT, DL, SubVecs[0], SubVecs[1], in visitVectorDeinterleave()
12617 EVT OutVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitVectorInterleave() local
12628 if (OutVT.isFixedLengthVector() && Factor == 2) { in visitVectorInterleave()
12630 SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVecs); in visitVectorInterleave()
[all …]
H A DDAGCombiner.cpp649 std::optional<EVT> OutVT = std::nullopt);
26283 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); in canCombineShuffleToExtendVectorInreg() local
26285 if ((LegalTypes && !TLI.isTypeLegal(OutVT)) || in canCombineShuffleToExtendVectorInreg()
26286 (LegalOperations && !TLI.isOperationLegalOrCustom(Opcode, OutVT))) in canCombineShuffleToExtendVectorInreg()
26290 return OutVT; in canCombineShuffleToExtendVectorInreg()
26327 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( in combineShuffleToAnyExtendVectorInreg() local
26329 if (!OutVT) in combineShuffleToAnyExtendVectorInreg()
26331 return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, N0)); in combineShuffleToAnyExtendVectorInreg()
26448 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( in combineShuffleToZeroExtendVectorInReg() local
26451 if (OutVT) in combineShuffleToZeroExtendVectorInReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp3155 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
3158 OutVT = MVT::i16; in truncateVectorWithNARROW()
3162 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithNARROW()
3172 SDValue Res = DAG.getNode(WebAssemblyISD::NARROW_U, DL, OutVT, Lo, Hi); in truncateVectorWithNARROW()
3195 EVT OutVT = N->getValueType(0); in performTruncateCombine() local
3196 if (!OutVT.isVector()) in performTruncateCombine()
3199 EVT OutSVT = OutVT.getVectorElementType(); in performTruncateCombine()
3203 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector())) in performTruncateCombine()
3208 OutVT.getScalarSizeInBits()); in performTruncateCombine()
3210 return truncateVectorWithNARROW(OutVT, In, DL, DAG); in performTruncateCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5763 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8), in getPermuteNode() local
5765 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1); in getPermuteNode()
6162 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits), in insertUnpackIfPrepared() local
6166 DL, OutVT, PackedOp); in insertUnpackIfPrepared()
6569 EVT OutVT = Op.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
6571 unsigned ToBits = OutVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
6581 int OutNumElts = OutVT.getVectorNumElements(); in lowerSIGN_EXTEND_VECTOR_INREG()
6615 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits), OutNumElts); in lowerSIGN_EXTEND_VECTOR_INREG() local
6621 PackedOp = DAG.getNode(Opcode, SDLoc(PackedOp), OutVT, PackedOp); in lowerSIGN_EXTEND_VECTOR_INREG()
6631 EVT OutVT = Op.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td7571 multiclass Neon_INS_elt_ext_pattern<ValueType VT128, ValueType VT64, ValueType OutVT,
7574 // VT64->OutVT
7575 def : Pat<(OutVT (vector_insert (OutVT V64:$src),
7582 def : Pat<(OutVT (scalar_to_vector (i32 (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))))),
7590 // VT128->OutVT
7591 def : Pat<(OutVT (vector_insert (OutVT V64:$src),
7598 def : Pat<(OutVT (scalar_to_vector (i32 (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))))),
H A DSVEInstrFormats.td2950 ValueType OutVT, ValueType InVT,
2953 …def : SVE_4_Op_Imm_Pat<OutVT, op, OutVT, InVT, InVT, i32, VectorIndexH32b_timm, !cast<Instruction>…
2986 multiclass sve2_fp_mla_long<bits<3> opc, string asm, ValueType OutVT,
2989 def : SVE_3_Op_Pat<OutVT, op, OutVT, InVT, InVT, !cast<Instruction>(NAME)>;
H A DAArch64ISelLowering.cpp21809 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); in getPTest() local
21810 SDValue TVal = DAG.getConstant(1, DL, OutVT); in getPTest()
21811 SDValue FVal = DAG.getConstant(0, DL, OutVT); in getPTest()
21831 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test); in getPTest()
26123 SDValue OutVT = DAG.getValueType(RetVT); in performGatherLoadCombine() local
26125 OutVT = DAG.getValueType(HwRetVt); in performGatherLoadCombine()
26130 Base, Offset, OutVT}; in performGatherLoadCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSSE.td3784 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3795 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3804 (OutVT (OpNode (ArgVT RC:$src1),
3809 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3820 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3829 (OutVT (OpNode (ArgVT RC:$src1),
H A DX86ISelLowering.cpp21047 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithPACK() local
21051 OutVT = MVT::i16; in truncateVectorWithPACK()
21058 OutVT = EVT::getVectorVT(Ctx, OutVT, 128 / OutVT.getSizeInBits()); in truncateVectorWithPACK()
21062 SDValue Res = DAG.getNode(Opcode, DL, OutVT, LHS, RHS); in truncateVectorWithPACK()
21082 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithPACK()
21088 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
21097 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
21103 int Scale = 64 / OutVT.getScalarSizeInBits(); in truncateVectorWithPACK()
21105 Res = DAG.getVectorShuffle(OutVT, DL, Res, Res, Mask); in truncateVectorWithPACK()
H A DX86InstrAVX512.td166 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
171 AVX512_maskable_common<O, F, OutVT, Outs,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8828 EVT OutVT = Op.getValueType(); in LowerINT_TO_FP() local
8829 if (OutVT.isVector() && OutVT.isFloatingPoint() && in LowerINT_TO_FP()