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Searched refs:OutR (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp415 RegisterSubReg OutR(Op0); in convertToPredForm() local
434 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
438 MRI->replaceRegWith(OutR.R, NewOutR); in convertToPredForm()
H A DHexagonBitSimplify.cpp2964 bool isShuffleOf(unsigned OutR, unsigned InpR) const;
3057 bool HexagonLoopRescheduling::isShuffleOf(unsigned OutR, unsigned InpR) const { in isShuffleOf() argument
3058 if (!BTP->has(OutR) || !BTP->has(InpR)) in isShuffleOf()
3060 const BitTracker::RegisterCell &OutC = BTP->lookup(OutR); in isShuffleOf()