| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNDPPCombine.cpp | 216 auto OrigOp = OrigMI.getOpcode(); in createDPPInst() local
217 if (ST->useRealTrue16Insts() && AMDGPU::isTrue16Inst(OrigOp)) { in createDPPInst()
222 auto DPPOp = getDPPOp(OrigOp, IsShrinkable); in createDPPInst()
227 int OrigOpE32 = AMDGPU::getVOPe32(OrigOp); in createDPPInst()
641 auto OrigOp = OrigMI.getOpcode(); in combineDPPMov() local
642 assert((TII->get(OrigOp).getSize() != 4 || !AMDGPU::isTrue16Inst(OrigOp)) && in combineDPPMov()
644 if (OrigOp == AMDGPU::REG_SEQUENCE) { in combineDPPMov()
675 ((TII->isVOP3P(OrigOp) || TII->isVOPC(OrigOp) || in combineDPPMov()
676 TII->isVOP3(OrigOp)) && in combineDPPMov()
678 TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) { in combineDPPMov()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | PredicateInfo.cpp | 490 Value *OrigOp) { in materializeStack() argument
504 RenameIter == RenameStack.begin() ? OrigOp : (RenameIter - 1)->Def; in materializeStack()
508 ? OrigOp in materializeStack()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypes.cpp | 520 SDValue OrigOp = N->getOperand(i); in AnalyzeNewNode() local
521 SDValue Op = OrigOp; in AnalyzeNewNode()
531 } else if (Op != OrigOp) { in AnalyzeNewNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 1702 X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]); in VerifyAndAdjustOperands() local
1706 (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg())) in VerifyAndAdjustOperands()
1712 if (!OrigOp.isMem()) in VerifyAndAdjustOperands()
1716 MCRegister OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands()
1723 return Error(OrigOp.getStartLoc(), in VerifyAndAdjustOperands()
1744 OrigOp.getStartLoc(), in VerifyAndAdjustOperands()
1749 FinalOp.Mem.Size = OrigOp.Mem.Size; in VerifyAndAdjustOperands()
1750 FinalOp.Mem.SegReg = OrigOp.Mem.SegReg; in VerifyAndAdjustOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 764 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 4882 auto *OrigOp = OrigFI.getOperand(0); in pushFreezeToPreventPoisonFromPropagating() local
4883 auto *OrigOpInst = dyn_cast<Instruction>(OrigOp); in pushFreezeToPreventPoisonFromPropagating()
4888 if (!OrigOpInst || !OrigOpInst->hasOneUse() || isa<PHINode>(OrigOp)) in pushFreezeToPreventPoisonFromPropagating()
4895 if (canCreateUndefOrPoison(cast<Operator>(OrigOp), in pushFreezeToPreventPoisonFromPropagating()
4917 return OrigOp; in pushFreezeToPreventPoisonFromPropagating()
4924 return OrigOp; in pushFreezeToPreventPoisonFromPropagating()
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaExpr.cpp | 14378 QualType Sema::CheckAddressOfOperand(ExprResult &OrigOp, SourceLocation OpLoc) { in CheckAddressOfOperand() argument
14379 if (const BuiltinType *PTy = OrigOp.get()->getType()->getAsPlaceholderType()){ in CheckAddressOfOperand()
14381 Expr *E = OrigOp.get()->IgnoreParens(); in CheckAddressOfOperand()
14385 << OrigOp.get()->getSourceRange(); in CheckAddressOfOperand()
14393 << OrigOp.get()->getSourceRange(); in CheckAddressOfOperand()
14405 << OrigOp.get()->getSourceRange(); in CheckAddressOfOperand()
14409 OrigOp = CheckPlaceholderExpr(OrigOp.get()); in CheckAddressOfOperand()
14410 if (OrigOp.isInvalid()) return QualType(); in CheckAddressOfOperand()
14413 if (OrigOp.get()->isTypeDependent()) in CheckAddressOfOperand()
14416 assert(!OrigOp.get()->hasPlaceholderType()); in CheckAddressOfOperand()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 526 SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV,
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| H A D | HexagonISelLoweringHVX.cpp | 1266 HexagonTargetLowering::extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, in extractHvxSubvectorReg() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | NewGVN.cpp | 2814 auto *OrigOp = &*Op; in makePossiblePHIOfOps() local
2819 if (Op != OrigOp && Op != I) in makePossiblePHIOfOps()
2828 (Op != OrigOp || OpIsSafeForPHIOfOps(Op, PHIBlock, VisitedOps)); in makePossiblePHIOfOps()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 248 Register OrigOp = MI.getOperand(1).getReg(); in matchFreezeOfSingleMaybePoisonOperand() local
250 if (!MRI.hasOneNonDBGUse(OrigOp)) in matchFreezeOfSingleMaybePoisonOperand()
253 MachineInstr *OrigDef = MRI.getUniqueVRegDef(OrigOp); in matchFreezeOfSingleMaybePoisonOperand()
265 if (canCreateUndefOrPoison(OrigOp, MRI, in matchFreezeOfSingleMaybePoisonOperand()
292 B.buildCopy(DstOp, OrigOp); in matchFreezeOfSingleMaybePoisonOperand()
309 replaceRegWith(MRI, DstOp, OrigOp); in matchFreezeOfSingleMaybePoisonOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 10564 static void processVCIXOperands(SDValue &OrigOp, in processVCIXOperands() argument
10567 promoteVCIXScalar(OrigOp, Operands, DAG); in processVCIXOperands()
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