| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNDPPCombine.cpp | 215 auto OrigOp = OrigMI.getOpcode(); in createDPPInst() local
216 auto DPPOp = getDPPOp(OrigOp, IsShrinkable); in createDPPInst()
221 int OrigOpE32 = AMDGPU::getVOPe32(OrigOp); in createDPPInst()
638 auto OrigOp = OrigMI.getOpcode(); in combineDPPMov() local
639 assert((TII->get(OrigOp).getSize() != 4 || !AMDGPU::isTrue16Inst(OrigOp)) && in combineDPPMov()
641 if (OrigOp == AMDGPU::REG_SEQUENCE) { in combineDPPMov()
672 ((TII->isVOP3P(OrigOp) || TII->isVOPC(OrigOp) || in combineDPPMov()
673 TII->isVOP3(OrigOp)) && in combineDPPMov()
675 TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) { in combineDPPMov()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | PredicateInfo.cpp | 529 Value *OrigOp) { in materializeStack() argument
543 RenameIter == RenameStack.begin() ? OrigOp : (RenameIter - 1)->Def; in materializeStack()
547 ? OrigOp in materializeStack()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypes.cpp | 517 SDValue OrigOp = N->getOperand(i); in AnalyzeNewNode() local
518 SDValue Op = OrigOp; in AnalyzeNewNode()
528 } else if (Op != OrigOp) { in AnalyzeNewNode()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 1679 X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]); in VerifyAndAdjustOperands() local
1683 (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg())) in VerifyAndAdjustOperands()
1689 if (!OrigOp.isMem()) in VerifyAndAdjustOperands()
1693 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands()
1700 return Error(OrigOp.getStartLoc(), in VerifyAndAdjustOperands()
1721 OrigOp.getStartLoc(), in VerifyAndAdjustOperands()
1726 FinalOp.Mem.Size = OrigOp.Mem.Size; in VerifyAndAdjustOperands()
1727 FinalOp.Mem.SegReg = OrigOp.Mem.SegReg; in VerifyAndAdjustOperands()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 729 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 4440 auto *OrigOp = OrigFI.getOperand(0); in pushFreezeToPreventPoisonFromPropagating() local
4441 auto *OrigOpInst = dyn_cast<Instruction>(OrigOp); in pushFreezeToPreventPoisonFromPropagating()
4446 if (!OrigOpInst || !OrigOpInst->hasOneUse() || isa<PHINode>(OrigOp)) in pushFreezeToPreventPoisonFromPropagating()
4453 if (canCreateUndefOrPoison(cast<Operator>(OrigOp), in pushFreezeToPreventPoisonFromPropagating()
4475 return OrigOp; in pushFreezeToPreventPoisonFromPropagating()
4482 return OrigOp; in pushFreezeToPreventPoisonFromPropagating()
|
| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaExpr.cpp | 13980 QualType Sema::CheckAddressOfOperand(ExprResult &OrigOp, SourceLocation OpLoc) { in CheckAddressOfOperand() argument
13981 if (const BuiltinType *PTy = OrigOp.get()->getType()->getAsPlaceholderType()){ in CheckAddressOfOperand()
13983 Expr *E = OrigOp.get()->IgnoreParens(); in CheckAddressOfOperand()
13987 << OrigOp.get()->getSourceRange(); in CheckAddressOfOperand()
13995 << OrigOp.get()->getSourceRange(); in CheckAddressOfOperand()
14007 << OrigOp.get()->getSourceRange(); in CheckAddressOfOperand()
14011 OrigOp = CheckPlaceholderExpr(OrigOp.get()); in CheckAddressOfOperand()
14012 if (OrigOp.isInvalid()) return QualType(); in CheckAddressOfOperand()
14015 if (OrigOp.get()->isTypeDependent()) in CheckAddressOfOperand()
14018 assert(!OrigOp.get()->hasPlaceholderType()); in CheckAddressOfOperand()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 509 SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV,
|
| H A D | HexagonISelLoweringHVX.cpp | 1255 HexagonTargetLowering::extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV,
1270 VecV = OrigOp; in extractHvxSubvectorReg()
1256 extractHvxSubvectorReg(SDValue OrigOp,SDValue VecV,SDValue IdxV,const SDLoc & dl,MVT ResTy,SelectionDAG & DAG) const extractHvxSubvectorReg() argument
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | NewGVN.cpp | 2776 auto *OrigOp = &*Op; in makePossiblePHIOfOps() local
2781 if (Op != OrigOp && Op != I) in makePossiblePHIOfOps()
2790 (Op != OrigOp || OpIsSafeForPHIOfOps(Op, PHIBlock, VisitedOps)); in makePossiblePHIOfOps()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 230 Register OrigOp = MI.getOperand(1).getReg(); in matchFreezeOfSingleMaybePoisonOperand() local
232 if (!MRI.hasOneNonDBGUse(OrigOp)) in matchFreezeOfSingleMaybePoisonOperand()
235 MachineInstr *OrigDef = MRI.getUniqueVRegDef(OrigOp); in matchFreezeOfSingleMaybePoisonOperand()
247 if (canCreateUndefOrPoison(OrigOp, MRI, in matchFreezeOfSingleMaybePoisonOperand()
274 B.buildCopy(DstOp, OrigOp); in matchFreezeOfSingleMaybePoisonOperand()
291 replaceRegWith(MRI, DstOp, OrigOp); in matchFreezeOfSingleMaybePoisonOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 9049 static void processVCIXOperands(SDValue &OrigOp, in processVCIXOperands()
9052 promoteVCIXScalar(OrigOp, Operands, DAG); in processVCIXOperands()
9047 processVCIXOperands(SDValue & OrigOp,SmallVectorImpl<SDValue> & Operands,SelectionDAG & DAG) processVCIXOperands() argument
|