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Searched refs:OrigIdx (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp107 SlotIndex OrigIdx, in allUsesAvailableAt() argument
109 OrigIdx = OrigIdx.getRegSlot(true); in allUsesAvailableAt()
124 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx); in allUsesAvailableAt()
131 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) in allUsesAvailableAt()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h198 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp8476 const unsigned OrigIdx = IdxC->getZExtValue(); in lowerINSERT_VECTOR_ELT()
8478 if (auto ShrunkVT = getSmallestVTForIndex(ContainerVT, OrigIdx, in lowerINSERT_VECTOR_ELT()
8492 unsigned RemIdx = OrigIdx % ElemsPerVReg; in lowerINSERT_VECTOR_ELT()
8493 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; in lowerINSERT_VECTOR_ELT()
8700 unsigned OrigIdx = IdxC->getZExtValue(); in lowerEXTRACT_VECTOR_ELT()
8703 unsigned RemIdx = OrigIdx % ElemsPerVReg; in lowerEXTRACT_VECTOR_ELT()
8704 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; in lowerEXTRACT_VECTOR_ELT()
10020 unsigned OrigIdx = Op.getConstantOperandVal(2); in lowerINSERT_SUBVECTOR()
10029 (OrigIdx != 0 || !Vec.isUndef())) { in lowerINSERT_SUBVECTOR()
10032 assert(OrigIdx in lowerINSERT_SUBVECTOR()
8474 const unsigned OrigIdx = IdxC->getZExtValue(); lowerINSERT_VECTOR_ELT() local
8698 unsigned OrigIdx = IdxC->getZExtValue(); lowerEXTRACT_VECTOR_ELT() local
10018 unsigned OrigIdx = Op.getConstantOperandVal(2); lowerINSERT_SUBVECTOR() local
10254 unsigned OrigIdx = Op.getConstantOperandVal(1); lowerEXTRACT_SUBVECTOR() local
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