Searched refs:Orders (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 739 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSDDbgValues()
775 Orders.push_back({DVOrder, DbgMI}); in ProcessSDDbgValues()
786 SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders, in ProcessSourceNode() argument
792 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
802 Orders.push_back({Order, NewInsn}); in ProcessSourceNode()
807 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
856 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
952 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen, NewInsn); in EmitSchedule()
964 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, Seen, in EmitSchedule()
981 llvm::stable_sort(Orders, less_first()); in EmitSchedule()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | InlineSpiller.cpp | 121 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1409 SmallVectorImpl<MachineDomTreeNode *> &Orders, in getVisitOrders() argument
1468 Orders.push_back(MDT.getNode(Root)); in getVisitOrders()
1470 MachineDomTreeNode *Node = Orders[idx++]; in getVisitOrders()
1473 Orders.push_back(Child); in getVisitOrders()
1475 } while (idx != Orders.size()); in getVisitOrders()
1476 assert(Orders.size() == WorkSet.size() && in getVisitOrders()
1480 LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n"); in getVisitOrders()
1481 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); in getVisitOrders()
1482 for (; RIt != Orders.rend(); RIt++) in getVisitOrders()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | ConstantHoisting.cpp | 259 SmallVector<BasicBlock *, 16> Orders; in findBestInsertionSet() local
260 Orders.push_back(Entry); in findBestInsertionSet()
261 while (Idx != Orders.size()) { in findBestInsertionSet()
262 BasicBlock *Node = Orders[Idx++]; in findBestInsertionSet()
265 Orders.push_back(ChildDomNode->getBlock()); in findBestInsertionSet()
276 InsertPtsMap.reserve(Orders.size() + 1); in findBestInsertionSet()
277 for (BasicBlock *Node : llvm::reverse(Orders)) { in findBestInsertionSet()
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 317 std::vector<SmallVector<Record *, 16>> Orders; variable
455 ArrayRef<Record *> getOrder(unsigned No = 0) const { return Orders[No]; }
458 unsigned getNumOrders() const { return Orders.size(); } in getNumOrders()
|
| H A D | CodeGenRegisters.cpp | 778 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
783 Orders[0].push_back((*Elements)[i]); in CodeGenRegisterClass()
795 Orders[1 + i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
881 Orders.resize(Super.Orders.size()); in inheritProperties()
882 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
883 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
884 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
885 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
|
| /freebsd/contrib/bmake/ |
| H A D | bmake.cat1 | 951 ::OO Orders the words lexicographically.
953 ::OOnn Orders the words numerically. A number followed by one of `k', `M'
958 ::OOrr Orders the words in reverse lexicographical order.
961 Orders the words in reverse numerical order.
|
| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 4827 llvm::AtomicOrdering Orders[5] = { in EmitBuiltinExpr() local
4841 Ptr, NewVal, Orders[i]); in EmitBuiltinExpr()
4892 llvm::AtomicOrdering Orders[3] = { in EmitBuiltinExpr() local
4902 Store->setOrdering(Orders[i]); in EmitBuiltinExpr()
|
| /freebsd/contrib/tzdata/ |
| H A D | europe | 384 # Summer Time Act, 1925 and Summer Time Orders, 1926 and 1947:
|