/freebsd/contrib/llvm-project/llvm/tools/llvm-tapi-diff/ |
H A D | DiffEngine.cpp |
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H A D | DiffEngine.h |
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable 59 return AO.Order[Pos]; 67 while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos])) 90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument 92 : Hints(std::move(Hints)), Order(Order), in AllocationOrder() 93 IterationLimit(HardHints ? 0 : static_cast<int>(Order.size())) {} in AllocationOrder() 102 assert(OrderLimit <= Order.size()); in getOrderLimitEnd() 111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
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H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local 37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create() 48 [&](MCPhysReg Hint) { return is_contained(Order, Hint); }) && in create() 50 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
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H A D | RegAllocGreedy.cpp | 398 AllocationOrder &Order, in tryAssign() argument 402 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in tryAssign() 419 if (Order.isHint(Hint)) { in tryAssign() 430 if (trySplitAroundHintReg(PhysHint, VirtReg, NewVRegs, Order)) in tryAssign() 447 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters); in tryAssign() 532 const AllocationOrder &Order, in getOrderLimit() argument 534 unsigned OrderLimit = Order.getOrder().size(); in getOrderLimit() 548 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) { in getOrderLimit() 578 AllocationOrder &Order, in tryEvict() argument 586 VirtReg, Order, CostPerUseLimit, FixedRegisters); in tryEvict() [all …]
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H A D | RegisterClassInfo.cpp | 133 if (!RCI.Order) in compute() 134 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute() 159 RCI.Order[N++] = PhysReg; in compute() 171 RCI.Order[N++] = PhysReg; in compute() 191 dbgs() << ' ' << printReg(RCI.Order[I], TRI); in compute()
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H A D | LocalStackSlotAllocation.cpp | 59 unsigned Order; member in __anon7165d95d0111::FrameRef 63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef() 66 return std::tie(LocalOffset, FrameIdx, Order) < in operator <() 67 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order); in operator <() 323 unsigned Order = 0; in insertFrameReferenceRegisters() local 351 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++)); in insertFrameReferenceRegisters()
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H A D | RegAllocEvictionAdvisor.cpp | 277 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument 283 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate() 295 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryFindEvictionCandidate()
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H A D | MLRegallocEvictAdvisor.cpp |
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H A D | MLRegAllocEvictAdvisor.cpp | 308 const AllocationOrder &Order, 324 const LiveInterval &VirtReg, const AllocationOrder &Order, 441 const LiveInterval &VirtReg, const AllocationOrder &Order, 667 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument 669 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate() 707 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryFindEvictionCandidate() 781 VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidate() 1088 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition() argument 1094 VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidatePosition() 1097 VirtReg, Order, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidatePosition() [all …]
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H A D | RegAllocGreedy.h | 331 const AllocationOrder &Order); 351 AllocationOrder &Order, 357 AllocationOrder &Order, 366 AllocationOrder &Order); 370 AllocationOrder &Order, MCRegister PhysReg,
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/freebsd/contrib/llvm-project/llvm/lib/Support/ |
H A D | DynamicLibrary.cpp | 81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup() argument 82 if (Order & SO_LoadOrder) { in LibLookup() 96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup() argument 97 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && in Lookup() 100 if (!Process || (Order & SO_LoadedFirst)) { in Lookup() 101 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup() 110 if (Order & SO_LoadedLast) { in Lookup() 111 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 766 void setIROrder(unsigned Order) { IROrder = Order; } 1129 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs) 1131 IROrder(Order), debugLoc(std::move(dl)) { 1160 SDLoc(const Instruction *I, int Order) : IROrder(Order) { 1161 assert(Order >= 0 && "bad IROrder"); 1308 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, 1310 : SDNode(ISD::ADDRSPACECAST, Order, dl, VTs), SrcAddrSpace(SrcAS), 1332 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, 1498 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL, 1500 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) { [all …]
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H A D | ScheduleDAG.h | 56 Order ///< Any other ordering dependency. enumerator 124 : Dep(S, Order), Contents(), Latency(0) { in SDep() 169 return getKind() == Order && (Contents.OrdKind == MayAliasMem in isNormalMemory() 175 return getKind() == Order && Contents.OrdKind == Barrier; in isBarrier() 187 return getKind() == Order && Contents.OrdKind == MustAliasMem; in isMustAlias() 195 return getKind() == Order && Contents.OrdKind >= Weak; in isWeak() 201 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial() 207 return getKind() == Order && Contents.OrdKind == Cluster; in isCluster() 491 case Order: in overlaps()
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H A D | RuntimeLibcallUtil.h | 72 Libcall getOutlineAtomicHelper(const Libcall (&LC)[5][4], AtomicOrdering Order, 77 Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT);
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H A D | RegisterClassInfo.h | 36 std::unique_ptr<MCPhysReg[]> Order; member 41 return ArrayRef(Order.get(), NumRegs);
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SDNodeDbgValue.h | 149 unsigned Order; variable 163 Var(Var), Expr(Expr), DL(DL), Order(O), IsIndirect(IsIndirect), in SDDbgValue() 219 unsigned getOrder() const { return Order; } in getOrder() 245 unsigned Order; variable 249 : Label(Label), DL(std::move(dl)), Order(O) {} in SDDbgLabel() 259 unsigned getOrder() const { return Order; } in getOrder()
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H A D | ScheduleDAGSDNodes.cpp | 740 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues() argument 763 if (Order != 0 && DVOrder != Order) in ProcessSDDbgValues() 788 unsigned Order = N->getIROrder(); in ProcessSourceNode() local 789 if (!Order || Seen.count(Order)) { in ProcessSourceNode() 801 Seen.insert(Order); in ProcessSourceNode() 802 Orders.push_back({Order, NewInsn}); in ProcessSourceNode() 807 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode() 992 unsigned Order = Orders[i].first; in EmitSchedule() local 997 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule() 1015 LastOrder = Order; in EmitSchedule() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | StructurizeCFG.cpp | 251 SmallVector<RegionNode *, 8> Order; member in __anone8c890770111::StructurizeCFG 380 Order.resize(std::distance(GraphTraits<Region *>::nodes_begin(ParentRegion), in INITIALIZE_PASS_DEPENDENCY() 382 if (Order.empty()) in INITIALIZE_PASS_DEPENDENCY() 390 unsigned I = 0, E = Order.size(); in INITIALIZE_PASS_DEPENDENCY() 409 Order[I++] = N.first; in INITIALIZE_PASS_DEPENDENCY() 424 Nodes.insert(Order.begin() + I, Order.begin() + E - 1); in INITIALIZE_PASS_DEPENDENCY() 427 EntryNode.first = Order[E - 1]; in INITIALIZE_PASS_DEPENDENCY() 534 for (RegionNode *RN : reverse(Order)) { in collectInfos() 852 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : in getNextFlow() 853 Order.back()->getEntry(); in getNextFlow() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints() argument 64 for (MCPhysReg Reg : Order) in addHints() 68 for (MCPhysReg Reg : Order) in addHints() 75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument 83 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints() 126 for (MCPhysReg OrderReg : Order) in getRegAllocationHints() 156 addHints(Order, Hints, RC, MRI); in getRegAllocationHints() 177 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI); in getRegAllocationHints()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64GenRegisterBankInfo.def | 149 ArrayRef<PartialMappingIdx> Order) { 150 if (Order.front() != FirstAlias) 152 if (Order.back() != LastAlias) 154 if (Order.front() > Order.back()) 157 PartialMappingIdx Previous = Order.front(); 159 for (const auto &Current : Order) {
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/freebsd/sys/contrib/device-tree/Bindings/media/ |
H A D | fsl-vdoa.txt | 1 Freescale Video Data Order Adapter 4 The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInsertDelayAlu.cpp | 247 SmallVector<const_iterator, 8> Order; in dump() local 248 Order.reserve(size()); in dump() 250 Order.push_back(I); in dump() 251 llvm::sort(Order, [](const const_iterator &A, const const_iterator &B) { in dump() 254 for (const_iterator I : Order) { in dump()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | CodeLayout.cpp | 1001 std::vector<uint64_t> Order; in applyExtTspLayout() 1002 Order.reserve(NumNodes); in applyExtTspLayout() 1005 Order.push_back(Node->Index); in applyExtTspLayout() 1006 return Order; in applyExtTspLayout() 1368 std::vector<uint64_t> Order; 1369 Order.reserve(NumNodes); 1372 Order.push_back(Node->Index); 1373 return Order; 1428 double codelayout::calcExtTspScore(ArrayRef<uint64_t> Order, 1434 for (size_t Idx = 1; Idx < Order 919 concatChains(std::vector<uint64_t> & Order) concatChains() argument 1008 calcExtTspScore(const std::vector<uint64_t> & Order,const std::vector<uint64_t> & NodeSizes,const std::vector<uint64_t> & NodeCounts,const std::vector<EdgeCountT> & EdgeCounts) calcExtTspScore() argument 1039 std::vector<uint64_t> Order(NodeSizes.size()); calcExtTspScore() local [all...] |
/freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGAtomic.cpp | 528 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp() argument 543 FailureOrder, Size, Order, Scope); in EmitAtomicOp() 549 FailureOrder, Size, Order, Scope); in EmitAtomicOp() 557 Val1, Val2, FailureOrder, Size, Order, Scope); in EmitAtomicOp() 571 FailureOrder, Size, Order, Scope); in EmitAtomicOp() 576 FailureOrder, Size, Order, Scope); in EmitAtomicOp() 591 Load->setAtomic(Order, Scope); in EmitAtomicOp() 606 Store->setAtomic(Order, Scope); in EmitAtomicOp() 730 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order, Scope); in EmitAtomicOp() 762 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp() argument [all …]
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