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Searched refs:Order (Results 1 – 25 of 179) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/tools/llvm-tapi-diff/
H A DDiffEngine.cpp
H A DDiffEngine.h
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAllocationOrder.h32 ArrayRef<MCPhysReg> Order; variable
59 return AO.Order[Pos];
67 while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos]))
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument
92 : Hints(std::move(Hints)), Order(Order), in AllocationOrder()
93 IterationLimit(HardHints ? 0 : static_cast<int>(Order.size())) {} in AllocationOrder()
102 assert(OrderLimit <= Order.size()); in getOrderLimitEnd()
111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
H A DAllocationOrder.cpp34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create()
48 [&](MCPhysReg Hint) { return is_contained(Order, Hint); }) && in create()
50 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
H A DRegisterClassInfo.cpp136 if (!RCI.Order) in compute()
137 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
167 RCI.Order[N++] = PhysReg; in compute()
179 RCI.Order[N++] = PhysReg; in compute()
199 dbgs() << ' ' << printReg(RCI.Order[I], TRI); in compute()
H A DRegAllocGreedy.cpp532 AllocationOrder &Order, in tryAssign() argument
536 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in tryAssign()
553 if (Order.isHint(Hint)) { in tryAssign()
564 if (trySplitAroundHintReg(PhysHint, VirtReg, NewVRegs, Order)) in tryAssign()
581 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters); in tryAssign()
666 const AllocationOrder &Order, in getOrderLimit() argument
668 unsigned OrderLimit = Order.getOrder().size(); in getOrderLimit()
682 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) { in getOrderLimit()
712 AllocationOrder &Order, in tryEvict() argument
720 VirtReg, Order, CostPerUseLimit, FixedRegisters); in tryEvict()
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H A DLocalStackSlotAllocation.cpp59 unsigned Order; member in __anon7165d95d0111::FrameRef
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
66 return std::tie(LocalOffset, FrameIdx, Order) < in operator <()
67 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order); in operator <()
321 unsigned Order = 0; in insertFrameReferenceRegisters() local
349 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++)); in insertFrameReferenceRegisters()
H A DMLRegallocEvictAdvisor.cpp
H A DMLRegAllocEvictAdvisor.cpp315 const AllocationOrder &Order,
331 const LiveInterval &VirtReg, const AllocationOrder &Order,
488 const LiveInterval &VirtReg, const AllocationOrder &Order,
744 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
746 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate()
784 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryFindEvictionCandidate()
858 VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidate()
1178 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition() argument
1184 VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidatePosition()
1187 VirtReg, Order, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidatePosition()
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H A DRegAllocEvictionAdvisor.cpp332 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
338 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate()
350 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryFindEvictionCandidate()
H A DRegAllocGreedy.h321 const AllocationOrder &Order);
341 AllocationOrder &Order,
347 AllocationOrder &Order,
357 AllocationOrder &Order);
361 AllocationOrder &Order, MCRegister PhysReg,
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DDynamicLibrary.cpp81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup() argument
82 if (Order & SO_LoadOrder) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup() argument
97 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && in Lookup()
100 if (Process == &Invalid || (Order & SO_LoadedFirst)) { in Lookup()
101 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
110 if (Order & SO_LoadedLast) { in Lookup()
111 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h786 void setIROrder(unsigned Order) { IROrder = Order; }
1203 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1205 IROrder(Order), debugLoc(std::move(dl)) {
1234 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1235 assert(Order >= 0 && "bad IROrder");
1383 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1385 : SDNode(ISD::ADDRSPACECAST, Order, dl, VTs), SrcAddrSpace(SrcAS),
1407 LLVM_ABI MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1584 AtomicSDNode(unsigned Order, const DebugLoc &dl, unsigned Opc, SDVTList VTL,
1586 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
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H A DScheduleDAG.h58 Order ///< Any other ordering dependency. enumerator
124 : Dep(S, Order), Contents(), Latency(0) { in SDep()
169 return getKind() == Order && (Contents.OrdKind == MayAliasMem in isNormalMemory()
175 return getKind() == Order && Contents.OrdKind == Barrier; in isBarrier()
187 return getKind() == Order && Contents.OrdKind == MustAliasMem; in isMustAlias()
195 return getKind() == Order && Contents.OrdKind >= Weak; in isWeak()
201 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial()
207 return getKind() == Order && Contents.OrdKind == Cluster; in isCluster()
495 case Order: in overlaps()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h150 unsigned Order; variable
164 Var(Var), Expr(Expr), DL(DL), Order(O), IsIndirect(IsIndirect), in SDDbgValue()
219 unsigned getOrder() const { return Order; } in getOrder()
245 unsigned Order; variable
249 : Label(Label), DL(std::move(dl)), Order(O) {} in SDDbgLabel()
259 unsigned getOrder() const { return Order; } in getOrder()
H A DScheduleDAGSDNodes.cpp739 InstrEmitter::VRBaseMapType &VRBaseMap, unsigned Order) { in ProcessSDDbgValues() argument
762 if (Order != 0 && DVOrder != Order) in ProcessSDDbgValues()
787 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
788 if (!Order || Seen.count(Order)) { in ProcessSourceNode()
800 Seen.insert(Order); in ProcessSourceNode()
801 Orders.push_back({Order, NewInsn}); in ProcessSourceNode()
806 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
995 unsigned Order = Orders[i].first; in EmitSchedule() local
1000 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1018 LastOrder = Order; in EmitSchedule()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp338 AtomicOrdering Order) const = 0;
405 AtomicOrdering Order) const override;
456 AtomicOrdering Order) const override;
544 AtomicOrdering Order) const override;
595 AtomicOrdering Order) const override;
1076 AtomicOrdering Order) const { in insertWait()
1429 AtomicOrdering Order) const { in insertWait()
1449 IsCrossAddrSpaceOrdering, Pos, Order); in insertWait()
1968 Position Pos, AtomicOrdering Order) const { in insertWait()
2289 Position Pos, AtomicOrdering Order) const { in insertWait()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXUtilities.h128 inline std::string OrderingToString(Ordering Order) { in OrderingToString() argument
129 switch (Order) { in OrderingToString()
148 static_cast<OrderingUnderlyingType>(Order))); in OrderingToString()
151 inline raw_ostream &operator<<(raw_ostream &O, Ordering Order) {
152 O << OrderingToString(Order);
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp289 SmallVector<RegionNode *, 8> Order; member in __anone8c890770111::StructurizeCFG
420 Order.resize(std::distance(GraphTraits<Region *>::nodes_begin(ParentRegion), in INITIALIZE_PASS_DEPENDENCY()
422 if (Order.empty()) in INITIALIZE_PASS_DEPENDENCY()
430 unsigned I = 0, E = Order.size(); in INITIALIZE_PASS_DEPENDENCY()
449 Order[I++] = N.first; in INITIALIZE_PASS_DEPENDENCY()
464 Nodes.insert(Order.begin() + I, Order.begin() + E - 1); in INITIALIZE_PASS_DEPENDENCY()
467 EntryNode.first = Order[E - 1]; in INITIALIZE_PASS_DEPENDENCY()
580 for (RegionNode *RN : reverse(Order)) { in collectInfos()
977 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : in getNextFlow()
978 Order.back()->getEntry(); in getNextFlow()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints() argument
63 for (MCPhysReg Reg : Order) in addHints()
67 for (MCPhysReg Reg : Order) in addHints()
74 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
82 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
125 for (MCPhysReg OrderReg : Order) in getRegAllocationHints()
155 addHints(Order, Hints, RC, MRI); in getRegAllocationHints()
176 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI); in getRegAllocationHints()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def149 ArrayRef<PartialMappingIdx> Order) {
150 if (Order.front() != FirstAlias)
152 if (Order.back() != LastAlias)
154 if (Order.front() > Order.back())
157 PartialMappingIdx Previous = Order.front();
159 for (const auto &Current : Order) {
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dfsl-vdoa.txt1 Freescale Video Data Order Adapter
4 The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGAtomic.cpp530 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp() argument
545 FailureOrder, Size, Order, Scope); in EmitAtomicOp()
551 FailureOrder, Size, Order, Scope); in EmitAtomicOp()
559 Val1, Val2, FailureOrder, Size, Order, Scope); in EmitAtomicOp()
573 FailureOrder, Size, Order, Scope); in EmitAtomicOp()
578 FailureOrder, Size, Order, Scope); in EmitAtomicOp()
593 Load->setAtomic(Order, Scope); in EmitAtomicOp()
610 Store->setAtomic(Order, Scope); in EmitAtomicOp()
735 CGF.Builder.getInt8(1), Order, Scope, E); in EmitAtomicOp()
746 Store->setAtomic(Order, Scope); in EmitAtomicOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVUtils.cpp673 Order.reserve(F.size()); in PartialOrderingVisitor()
675 Order.emplace_back(BB); in PartialOrderingVisitor()
677 std::sort(Order.begin(), Order.end(), [&](const auto &LHS, const auto &RHS) { in PartialOrderingVisitor()
697 auto It = Order.begin(); in partialOrderVisit()
698 while (It != Order.end() && *It != &Start) in partialOrderVisit()
703 assert(It != Order.end()); in partialOrderVisit()
707 for (; It != Order.end(); ++It) { in partialOrderVisit()
726 std::vector<BasicBlock *> Order; in sortBlocks() local
727 Order.reserve(F.size()); in sortBlocks()
730 llvm::append_range(Order, RPOT); in sortBlocks()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DCodeLayout.cpp1001 std::vector<uint64_t> Order; in concatChains() local
1002 Order.reserve(NumNodes); in concatChains()
1005 Order.push_back(Node->Index); in concatChains()
1006 return Order; in concatChains()
1368 std::vector<uint64_t> Order; in concatChains() local
1369 Order.reserve(NumNodes); in concatChains()
1372 Order.push_back(Node->Index); in concatChains()
1373 return Order; in concatChains()
1428 double codelayout::calcExtTspScore(ArrayRef<uint64_t> Order, in calcExtTspScore() argument
1433 for (uint64_t Idx = 1; Idx < Order.size(); Idx++) in calcExtTspScore()
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