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Searched refs:OperandSemantics (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td1114 // Should be in sync with the OperandSemantics defined in SIDefines.h
1115 def OperandSemantics {
1128 int immWidth, int OperandSemantics>
1131 ", " # immWidth # ", " # OperandSemantics # ">";
1134 def SSrc_b16 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_INT16", 16, OperandSemantics.INT>;
1135 def SSrc_bf16: SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>;
1136 def SSrc_f16 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_FP16", 16, OperandSemantics.FP16>;
1137 def SSrc_b32 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_INT32", 32, OperandSemantics.INT>;
1138 def SSrc_f32 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_FP32", 32, OperandSemantics.FP32>;
1139 def SSrc_b64 : SrcRegOrImm9 <SReg_64, "OPW64", "OPERAND_REG_IMM_INT64", 64, OperandSemantics.INT>;
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H A DSIDefines.h274 enum OperandSemantics : unsigned { enum
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h242 AMDGPU::OperandSemantics Sema);
250 AMDGPU::OperandSemantics Sema = AMDGPU::OperandSemantics::INT) const;
255 AMDGPU::OperandSemantics Sema = AMDGPU::OperandSemantics::INT) const;
263 AMDGPU::OperandSemantics Sema) const;
H A DAMDGPUDisassembler.cpp187 AMDGPU::OperandSemantics Sema, in decodeSrcOp()
208 false, 0, AMDGPU::OperandSemantics::INT, Decoder); in decodeAV10()
217 AMDGPU::OperandSemantics::INT, Decoder); in decodeSrcReg9()
227 AMDGPU::OperandSemantics::INT, Decoder); in decodeSrcA9()
237 AMDGPU::OperandSemantics::INT, Decoder); in decodeSrcAV10()
246 unsigned OperandSemantics>
251 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); in decodeSrcRegOrImm9()
257 unsigned OperandSemantics>
262 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); in decodeSrcRegOrImmA9()
266 unsigned OperandSemantics>
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