| /freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/ |
| H A D | aarch32.h | 195 /// OpcodeMask - Mask with all bits set that encode the op-code
211 static constexpr uint32_t OpcodeMask = 0x0f000000;
215 static constexpr uint32_t OpcodeMask = 0x0e000000;
223 static constexpr uint32_t OpcodeMask = 0x0ff00000;
238 static constexpr HalfWords OpcodeMask{0xf800, 0x9000};
244 static constexpr HalfWords OpcodeMask{0xf800, 0xc000};
251 static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000};
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.h | 147 const SmallBitVector &OpcodeMask,
278 const SmallBitVector &OpcodeMask) const;
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| H A D | X86TargetTransformInfo.cpp | 1519 unsigned Opcode1, const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
1521 if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) in getAltInstrCost()
6076 const SmallBitVector &OpcodeMask) const { in isLegalAltInstr()
6085 assert(OpcodeMask.size() == NumElements && "Mask and VecTy are incompatible"); in isLegalAltInstr()
6091 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfo.h | 822 const SmallBitVector &OpcodeMask) const;
1301 const SmallBitVector &OpcodeMask,
1921 const SmallBitVector &OpcodeMask) const = 0;
2041 const SmallBitVector &OpcodeMask,
2436 const SmallBitVector &OpcodeMask) const override { in isLegalAltInstr() argument
2437 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
2688 const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
2690 return Impl.getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
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| H A D | TargetTransformInfoImpl.h | 314 const SmallBitVector &OpcodeMask) const { in isLegalAltInstr() argument
591 const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
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| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | aarch32.cpp | 262 return (Wd & FixupInfo<K>::OpcodeMask) == FixupInfo<K>::Opcode; in readAddendThumb()
267 return (Hi & FixupInfo<K>::OpcodeMask.Hi) == FixupInfo<K>::Opcode.Hi && in readAddendThumb()
268 (Lo & FixupInfo<K>::OpcodeMask.Lo) == FixupInfo<K>::Opcode.Lo; in readAddendThumb()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 490 const SmallBitVector &OpcodeMask) const { in isLegalAltInstr()
491 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
926 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const { in getAltInstrCost() argument
928 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 1035 SmallBitVector OpcodeMask(VL.size(), false); in getAltInstrMask() local
1038 OpcodeMask.set(Lane); in getAltInstrMask()
1039 return OpcodeMask; in getAltInstrMask()
5275 SmallBitVector OpcodeMask(getAltInstrMask(TE->Scalars, Opcode0, Opcode1)); in reorderTopToBottom() local
5277 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
6186 SmallBitVector OpcodeMask(getAltInstrMask(VL, Opcode0, Opcode1)); in areAltOperandsProfitable() local
6189 Opcode0, Opcode1, OpcodeMask)) in areAltOperandsProfitable()
9980 SmallBitVector OpcodeMask(getAltInstrMask(E->Scalars, Opcode0, Opcode1)); in getEntryCost() local
9983 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in getEntryCost()
9985 VecTy, Opcode0, Opcode1, OpcodeMask, CostKin in getEntryCost()
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