| /freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 112 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
114 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12); in Decode_1000iiii_iiiiiiii()
117 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind"); in Decode_1000iiii_iiiiiiii()
159 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
161 SW.startLine() << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_10110001_0000iiii()
162 (Opcode1 & 0xf0) ? "spare" : "pop "); in Decode_10110001_0000iiii()
163 if (((Opcode1 & 0xf0) == 0x00) && Opcode1) in Decode_10110001_0000iiii()
164 PrintGPR((Opcode1 & 0x0f)); in Decode_10110001_0000iiii()
187 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
188 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_10110011_sssscccc()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.h | 146 unsigned Opcode1,
277 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
|
| H A D | X86TargetTransformInfo.cpp | 1519 unsigned Opcode1, const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
1521 if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) in getAltInstrCost()
6075 unsigned Opcode1, in isLegalAltInstr() argument
6091 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
|
| H A D | X86ISelLowering.cpp | 41262 unsigned Opcode1 = N1.getOpcode(); in combineTargetShuffle() local
41263 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB || in combineTargetShuffle()
41264 Opcode1 == ISD::FDIV) { in combineTargetShuffle()
41268 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) { in combineTargetShuffle()
41275 SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11); in combineTargetShuffle()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfo.h | 821 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1300 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1920 unsigned Opcode1,
2040 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
2435 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
2437 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
2687 unsigned Opcode1, in getAltInstrCost() argument
2690 return Impl.getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
|
| H A D | TargetTransformInfoImpl.h | 313 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
590 unsigned Opcode1, in getAltInstrCost() argument
|
| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 489 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
491 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
925 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in getAltInstrCost() argument
928 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 852 bool TargetInstrInfo::areOpcodesEqualOrInverse(unsigned Opcode1, in areOpcodesEqualOrInverse() argument
854 return Opcode1 == Opcode2 || getInverseOpcode(Opcode1) == Opcode2; in areOpcodesEqualOrInverse()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | Reassociate.cpp | 171 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1, in isReassociableOp() argument
175 (BO->getOpcode() == Opcode1 || BO->getOpcode() == Opcode2)) in isReassociableOp()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1266 bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const;
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 1032 /// Opcode1.
1034 unsigned Opcode1) { in getAltInstrMask() argument
1037 if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1) in getAltInstrMask()
5274 unsigned Opcode1 = TE->getAltOpcode(); in reorderTopToBottom() local
5275 SmallBitVector OpcodeMask(getAltInstrMask(TE->Scalars, Opcode0, Opcode1)); in reorderTopToBottom()
5277 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
6185 unsigned Opcode1 = S.getAltOpcode(); in areAltOperandsProfitable() local
6186 SmallBitVector OpcodeMask(getAltInstrMask(VL, Opcode0, Opcode1)); in areAltOperandsProfitable()
6189 Opcode0, Opcode1, OpcodeMask)) in areAltOperandsProfitable()
9979 unsigned Opcode1 in getEntryCost() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4283 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument
4292 int Scale1 = AArch64InstrInfo::getMemScale(Opcode1); in shouldClusterFI()
|
| H A D | AArch64ISelLowering.cpp | 17662 unsigned Opcode1 = SUB->getOperand(1).getOpcode(); in performVecReduceAddCombineWithUADDLP() local
17670 if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) { in performVecReduceAddCombineWithUADDLP()
17672 } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) { in performVecReduceAddCombineWithUADDLP()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5590 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); in isSaturatingMinMax() local
5591 if (!Opcode1 || Opcode0 == Opcode1) in isSaturatingMinMax()
|