| /freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 112 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
114 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12); in Decode_1000iiii_iiiiiiii()
117 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind"); in Decode_1000iiii_iiiiiiii()
159 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
161 SW.startLine() << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_10110001_0000iiii()
162 (Opcode1 & 0xf0) ? "spare" : "pop "); in Decode_10110001_0000iiii()
163 if (((Opcode1 & 0xf0) == 0x00) && Opcode1) in Decode_10110001_0000iiii()
164 PrintGPR((Opcode1 & 0x0f)); in Decode_10110001_0000iiii()
187 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
188 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_10110011_sssscccc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.h | 147 unsigned Opcode1,
289 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
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| H A D | X86InstrAMX.td | 631 multiclass AMXAVX512_BASE<bits<8> Opcode1, bits<8> Opcode2, string Opstr,
635 def rre : I<Opcode1, MRMSrcReg4VOp3, (outs VR512:$dst),
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| H A D | X86TargetTransformInfo.cpp | 1518 unsigned Opcode1, const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
1520 if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) in getAltInstrCost()
6439 unsigned Opcode1, in isLegalAltInstr() argument
6455 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
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| H A D | X86ISelLowering.cpp | 42820 unsigned Opcode1 = N1.getOpcode(); in combineTargetShuffle() local
42821 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB || in combineTargetShuffle()
42822 Opcode1 == ISD::FDIV) { in combineTargetShuffle()
42826 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) { in combineTargetShuffle()
42833 SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11); in combineTargetShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 499 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
501 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
979 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in getAltInstrCost() argument
982 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfo.h | 865 unsigned Opcode1,
1392 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
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| H A D | TargetTransformInfoImpl.h | 364 unsigned Opcode1, in isLegalAltInstr() argument
706 unsigned Opcode1, in getAltInstrCost() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 929 bool TargetInstrInfo::areOpcodesEqualOrInverse(unsigned Opcode1, in areOpcodesEqualOrInverse() argument
931 return Opcode1 == Opcode2 || getInverseOpcode(Opcode1) == Opcode2; in areOpcodesEqualOrInverse()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | Reassociate.cpp | 171 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1, in isReassociableOp() argument
175 (BO->getOpcode() == Opcode1 || BO->getOpcode() == Opcode2)) in isReassociableOp()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1332 bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 1633 unsigned Opcode0, unsigned Opcode1) { in getAltInstrMask() argument
1639 if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1) in getAltInstrMask()
7151 unsigned Opcode1 = TE->getAltOpcode(); in reorderTopToBottom() local
7153 getAltInstrMask(TE->Scalars, ScalarTy, Opcode0, Opcode1)); in reorderTopToBottom()
7155 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
8828 unsigned Opcode1 = S.getAltOpcode(); in areAltOperandsProfitable() local
8829 SmallBitVector OpcodeMask(getAltInstrMask(VL, ScalarTy, Opcode0, Opcode1)); in areAltOperandsProfitable()
8832 Opcode1, OpcodeMask)) in areAltOperandsProfitable()
9686 unsigned Opcode1 = LocalState.getAltOpcode(); in canBuildSplitNode() local
9687 SmallBitVector OpcodeMask(getAltInstrMask(VL, ScalarTy, Opcode0, Opcode1)); in canBuildSplitNode()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4868 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument
4877 int Scale1 = AArch64InstrInfo::getMemScale(Opcode1); in shouldClusterFI()
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| H A D | AArch64ISelLowering.cpp | 18133 unsigned Opcode1 = SUB->getOperand(1).getOpcode(); in performVecReduceAddCombineWithUADDLP() local
18141 if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) { in performVecReduceAddCombineWithUADDLP()
18143 } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) { in performVecReduceAddCombineWithUADDLP()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5965 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); in isSaturatingMinMax() local
5966 if (!Opcode1 || Opcode0 == Opcode1) in isSaturatingMinMax()
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