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Searched refs:Opcode0 (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/
H A DARMEHABIPrinter.h111 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
114 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12); in Decode_1000iiii_iiiiiiii()
117 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind"); in Decode_1000iiii_iiiiiiii()
158 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
161 SW.startLine() << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_10110001_0000iiii()
186 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
188 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_10110011_sssscccc()
209 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_11000110_sssscccc() local
211 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_11000110_sssscccc()
219 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_11000111_0000iiii() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.h146 InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
289 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
H A DX86TargetTransformInfo.cpp1517 X86TTIImpl::getAltInstrCost(VectorType *VecTy, unsigned Opcode0, in getAltInstrCost() argument
1520 if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) in getAltInstrCost()
6438 bool X86TTIImpl::isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, in isLegalAltInstr() argument
6455 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
H A DX86ISelLowering.cpp40843 unsigned Opcode0 = BC0.getOpcode(); in canonicalizeShuffleMaskWithHorizOp() local
40845 return V.getOpcode() != Opcode0 || V.getValueType() != VT0; in canonicalizeShuffleMaskWithHorizOp()
40849 bool isHoriz = (Opcode0 == X86ISD::FHADD || Opcode0 == X86ISD::HADD || in canonicalizeShuffleMaskWithHorizOp()
40850 Opcode0 == X86ISD::FHSUB || Opcode0 == X86ISD::HSUB); in canonicalizeShuffleMaskWithHorizOp()
40851 bool isPack = (Opcode0 == X86ISD::PACKSS || Opcode0 == X86ISD::PACKUS); in canonicalizeShuffleMaskWithHorizOp()
40886 if (Src1.getOpcode() == Opcode0 && Src0->isOnlyUserOf(Src1.getNode())) in canonicalizeShuffleMaskWithHorizOp()
40895 SDValue LHS = DAG.getNode(Opcode0, DL, SrcVT, M0, M1); in canonicalizeShuffleMaskWithHorizOp()
40896 SDValue RHS = DAG.getNode(Opcode0, DL, SrcVT, M2, M3); in canonicalizeShuffleMaskWithHorizOp()
40897 return DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
40927 SDValue Res = DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp499 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
501 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
979 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in getAltInstrCost() argument
982 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h864 LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0,
1392 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
H A DTargetTransformInfoImpl.h363 virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, in isLegalAltInstr() argument
705 virtual InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, in getAltInstrCost() argument
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp1633 unsigned Opcode0, unsigned Opcode1) { in getAltInstrMask() argument
7150 unsigned Opcode0 = TE->getOpcode(); in reorderTopToBottom() local
7153 getAltInstrMask(TE->Scalars, ScalarTy, Opcode0, Opcode1)); in reorderTopToBottom()
7155 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
8827 unsigned Opcode0 = S.getOpcode(); in areAltOperandsProfitable() local
8829 SmallBitVector OpcodeMask(getAltInstrMask(VL, ScalarTy, Opcode0, Opcode1)); in areAltOperandsProfitable()
8831 if (TTI->isLegalAltInstr(getWidenedType(ScalarTy, VL.size()), Opcode0, in areAltOperandsProfitable()
9685 unsigned Opcode0 = LocalState.getOpcode(); in canBuildSplitNode() local
9687 SmallBitVector OpcodeMask(getAltInstrMask(VL, ScalarTy, Opcode0, Opcode1)); in canBuildSplitNode()
9693 TTI->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask) || in canBuildSplitNode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2980 unsigned Opcode0 = C.Op0.getOpcode(); in shouldSwapCmpOperands() local
2981 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND) in shouldSwapCmpOperands()
2983 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND) in shouldSwapCmpOperands()
2985 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::AND && in shouldSwapCmpOperands()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp5911 unsigned Opcode0 = isSignedMinMax(N0, N1, N2, N3, CC); in isSaturatingMinMax() local
5912 if (!Opcode0) in isSaturatingMinMax()
5917 if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) { in isSaturatingMinMax()
5966 if (!Opcode1 || Opcode0 == Opcode1) in isSaturatingMinMax()
5969 ConstantSDNode *MinCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N1 : N01); in isSaturatingMinMax()
5970 ConstantSDNode *MaxCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N01 : N1); in isSaturatingMinMax()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18132 unsigned Opcode0 = SUB->getOperand(0).getOpcode(); in performVecReduceAddCombineWithUADDLP() local
18141 if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) { in performVecReduceAddCombineWithUADDLP()
18143 } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) { in performVecReduceAddCombineWithUADDLP()