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Searched refs:Opcode0 (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/
H A DARMEHABIPrinter.h111 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
114 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12); in Decode_1000iiii_iiiiiiii()
117 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind"); in Decode_1000iiii_iiiiiiii()
158 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
161 SW.startLine() << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_10110001_0000iiii()
186 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
188 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_10110011_sssscccc()
209 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_11000110_sssscccc() local
211 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_11000110_sssscccc()
219 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_11000111_0000iiii() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.h145 InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
277 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
H A DX86TargetTransformInfo.cpp1518 X86TTIImpl::getAltInstrCost(VectorType *VecTy, unsigned Opcode0, in getAltInstrCost() argument
1521 if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) in getAltInstrCost()
6074 bool X86TTIImpl::isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, in isLegalAltInstr() argument
6091 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
H A DX86ISelLowering.cpp39382 unsigned Opcode0 = BC0.getOpcode(); in canonicalizeShuffleMaskWithHorizOp() local
39384 return V.getOpcode() != Opcode0 || V.getValueType() != VT0; in canonicalizeShuffleMaskWithHorizOp()
39388 bool isHoriz = (Opcode0 == X86ISD::FHADD || Opcode0 == X86ISD::HADD || in canonicalizeShuffleMaskWithHorizOp()
39389 Opcode0 == X86ISD::FHSUB || Opcode0 == X86ISD::HSUB); in canonicalizeShuffleMaskWithHorizOp()
39390 bool isPack = (Opcode0 == X86ISD::PACKSS || Opcode0 == X86ISD::PACKUS); in canonicalizeShuffleMaskWithHorizOp()
39425 if (Src1.getOpcode() == Opcode0 && Src0->isOnlyUserOf(Src1.getNode())) in canonicalizeShuffleMaskWithHorizOp()
39434 SDValue LHS = DAG.getNode(Opcode0, DL, SrcVT, M0, M1); in canonicalizeShuffleMaskWithHorizOp()
39435 SDValue RHS = DAG.getNode(Opcode0, DL, SrcVT, M2, M3); in canonicalizeShuffleMaskWithHorizOp()
39436 return DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
39466 SDValue Res = DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h821 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1300 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1919 virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0,
2040 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
2435 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
2437 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
2686 InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, in getAltInstrCost() argument
2690 return Impl.getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
H A DTargetTransformInfoImpl.h313 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
589 InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, in getAltInstrCost() argument
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp489 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
491 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
925 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in getAltInstrCost() argument
928 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp1031 /// \returns a bitset for selecting opcodes. false for Opcode0 and true for
1033 SmallBitVector getAltInstrMask(ArrayRef<Value *> VL, unsigned Opcode0, in getAltInstrMask() argument
5273 unsigned Opcode0 = TE->getOpcode(); in reorderTopToBottom() local
5275 SmallBitVector OpcodeMask(getAltInstrMask(TE->Scalars, Opcode0, Opcode1)); in reorderTopToBottom()
5277 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
6184 unsigned Opcode0 = S.getOpcode(); in areAltOperandsProfitable() local
6186 SmallBitVector OpcodeMask(getAltInstrMask(VL, Opcode0, Opcode1)); in areAltOperandsProfitable()
6189 Opcode0, Opcode1, OpcodeMask)) in areAltOperandsProfitable()
9978 unsigned Opcode0 = E->getOpcode(); in getEntryCost() local
9980 SmallBitVector OpcodeMask(getAltInstrMask(E->Scalars, Opcode0, Opcode in getEntryCost()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2629 unsigned Opcode0 = C.Op0.getOpcode(); in shouldSwapCmpOperands() local
2630 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND) in shouldSwapCmpOperands()
2632 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND) in shouldSwapCmpOperands()
2634 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::AND && in shouldSwapCmpOperands()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp5536 unsigned Opcode0 = isSignedMinMax(N0, N1, N2, N3, CC); in isSaturatingMinMax() local
5537 if (!Opcode0) in isSaturatingMinMax()
5542 if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) { in isSaturatingMinMax()
5591 if (!Opcode1 || Opcode0 == Opcode1) in isSaturatingMinMax()
5594 ConstantSDNode *MinCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N1 : N01); in isSaturatingMinMax()
5595 ConstantSDNode *MaxCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N01 : N1); in isSaturatingMinMax()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp17661 unsigned Opcode0 = SUB->getOperand(0).getOpcode(); in performVecReduceAddCombineWithUADDLP() local
17670 if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) { in performVecReduceAddCombineWithUADDLP()
17672 } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) { in performVecReduceAddCombineWithUADDLP()