| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrVIS.td | 18 class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
24 class VISInstID<bits<9> opfval, string OpcStr>
27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
36 class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
39 !strconcat(OpcStr, " $rs1, $rd"), []>;
43 class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
46 !strconcat(OpcStr, " $rs2, $rd"), []>;
50 class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
53 !strconcat(OpcStr, " $rd"), []>;
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| H A D | SparcInstrInfo.td | 404 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
409 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
414 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
421 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
424 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
428 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
433 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
437 !strconcat(OpcStr, " [$addr], $rd"),
442 !strconcat(OpcStr, " [$addr], $rd"),
449 multiclass LoadASI<string OpcStr, bits<6> Op3Val, RegisterClass RC> {
[all …]
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| H A D | SparcInstrFormats.td | 235 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
239 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
243 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
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| H A D | SparcInstr64Bit.td | 357 multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
358 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
360 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.td | 208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
210 !strconcat(OpcStr, " $dst, $b, $c"),
213 !strconcat(OpcStr, " $dst, $b, $c"),
217 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
219 !strconcat(OpcStr, " $dst, $b, $c"), []>;
221 !strconcat(OpcStr, " $dst, $b, $c"), []>;
224 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
227 !strconcat(OpcStr, " $dst, $b, $c"),
230 !strconcat(OpcStr, " $dst, $b, $c"),
234 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.td | 212 // The instructions are named "<OpcStr><Width>" (e.g. "add.s64").
213 multiclass I3<string OpcStr, SDNode OpNode> {
216 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
220 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
224 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
228 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
232 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
236 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
240 class I16x2<string OpcStr, SDNode OpNode> :
242 !strconcat(OpcStr, "16x2 \t$dst, $a, $b;"),
[all …]
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| H A D | NVPTXIntrinsics.td | 606 // We need a full string for OpcStr here because we need to deal with case like
608 class F_MATH_1<string OpcStr, NVPTXRegClass target_regclass,
611 OpcStr,
615 // We need a full string for OpcStr here because we need to deal with the case
617 class F_MATH_2<string OpcStr, NVPTXRegClass t_regclass,
622 OpcStr,
626 class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
631 OpcStr,
1539 string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
1542 !strconcat("atom", SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b;"),
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.td | 863 string OpcStr, PatFrag OpNode>
867 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)",
881 string OpcStr, PatFrag OpNode>
885 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)",
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaOverload.cpp | 14805 StringRef OpcStr = BinaryOperator::getOpcodeStr(Opc); in CreateOverloadedBinOp() local
14834 CandidateSet.NoteCandidates(*this, Args, Cands, OpcStr, OpLoc); in CreateOverloadedBinOp()
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