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Searched refs:Opc0 (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp2370 BinaryOperator::BinaryOps Opc0 = B0->getOpcode(); in foldSelectShuffle() local
2373 if (ConstantsAreOp1 && Opc0 != Opc1) { in foldSelectShuffle()
2377 if (Opc0 == Instruction::Shl || Opc1 == Instruction::Shl) in foldSelectShuffle()
2381 Opc0 = AltB0.Opcode; in foldSelectShuffle()
2390 if (Opc0 != Opc1 || !C0 || !C1) in foldSelectShuffle()
2394 BinaryOperator::BinaryOps BOpc = Opc0; in foldSelectShuffle()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp84 unsigned Opc0 = N0->getMachineOpcode(); in nodesHaveSameOperandValue() local
87 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
242 unsigned Opc0 = Load0->getMachineOpcode(); in areLoadsFromSameBasePtr() local
246 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
250 if (!get(Opc0).getNumDefs() || !get(Opc1).getNumDefs()) in areLoadsFromSameBasePtr()
253 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
266 int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
275 Offset0Idx -= get(Opc0).NumDefs; in areLoadsFromSameBasePtr()
282 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
284 if (!AMDGPU::hasNamedOperand(Opc0, AMDGPU::OpName::sbase) || in areLoadsFromSameBasePtr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp26392 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
26400 Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26426 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
26434 Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26469 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
26479 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
26503 DAG.getNode(IntrData->Opc0, dl, VT, Src), Mask, PassThru, in LowerINTRINSIC_WO_CHAIN()
26514 Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26545 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, in LowerINTRINSIC_WO_CHAIN()
26553 unsigned Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
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H A DX86IntrinsicsInfo.h85 uint16_t Opc0; member
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp7946 unsigned Opc0 = N0.getOpcode(); in isBSwapHWordElement() local
7947 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) in isBSwapHWordElement()
7954 else if (Opc0 == ISD::AND) in isBSwapHWordElement()
7968 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { in isBSwapHWordElement()
7982 if (Opc0 != ISD::SRL) in isBSwapHWordElement()
7990 if (Opc0 != ISD::SHL) in isBSwapHWordElement()
11404 unsigned Opc0 = Op0.getOpcode(); in foldABSToABD() local
11408 if (Opc0 != Op1.getOpcode() || in foldABSToABD()
11409 (Opc0 != ISD::ZERO_EXTEND && Opc0 != ISD::SIGN_EXTEND && in foldABSToABD()
11410 Opc0 != ISD::SIGN_EXTEND_INREG)) { in foldABSToABD()
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