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Searched refs:Opc (Results 1 – 25 of 370) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp47 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
69 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
93 Opc = Mips::MOVE16_MM; in copyPhysReg()
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
97 Opc = Mips::CFC1; in copyPhysReg()
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H A DMips16InstrInfo.cpp73 unsigned Opc = 0; in copyPhysReg() local
77 Opc = Mips::MoveR3216; in copyPhysReg()
80 Opc = Mips::Move32R16; in copyPhysReg()
83 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
86 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
88 assert(Opc && "Cannot copy registers"); in copyPhysReg()
90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
115 unsigned Opc = 0; in storeRegToStack() local
117 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
118 assert(Opc && "Register class not handled!"); in storeRegToStack()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp788 unsigned Opc; in SelectAddrSpaceCast() local
792 Opc = TM.is64Bit() ? NVPTX::cvta_global_64 : NVPTX::cvta_global; in SelectAddrSpaceCast()
795 Opc = TM.is64Bit() ? (TM.getPointerSizeInBits(SrcAddrSpace) == 32 in SelectAddrSpaceCast()
801 Opc = TM.is64Bit() ? (TM.getPointerSizeInBits(SrcAddrSpace) == 32 in SelectAddrSpaceCast()
807 Opc = TM.is64Bit() ? (TM.getPointerSizeInBits(SrcAddrSpace) == 32 in SelectAddrSpaceCast()
813 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), in SelectAddrSpaceCast()
820 unsigned Opc; in SelectAddrSpaceCast() local
824 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_64 : NVPTX::cvta_to_global; in SelectAddrSpaceCast()
827 Opc = TM.is64Bit() ? (TM.getPointerSizeInBits(DstAddrSpace) == 32 in SelectAddrSpaceCast()
833 Opc = TM.is64Bit() ? (TM.getPointerSizeInBits(DstAddrSpace) == 32 in SelectAddrSpaceCast()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h126 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
584 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
585 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
591 static inline bool isVPTOpcode(int Opc) { in isVPTOpcode() argument
592 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || in isVPTOpcode()
593 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || in isVPTOpcode()
594 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || in isVPTOpcode()
595 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || in isVPTOpcode()
596 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || in isVPTOpcode()
597 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || in isVPTOpcode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.h148 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { in GetDefaultP2AlignAny() argument
149 switch (Opc) { in GetDefaultP2AlignAny()
279 inline unsigned GetDefaultP2Align(unsigned Opc) { in GetDefaultP2Align() argument
280 auto Align = GetDefaultP2AlignAny(Opc); in GetDefaultP2Align()
287 inline bool isConst(unsigned Opc) { in isConst() argument
288 switch (Opc) { in isConst()
315 inline bool isScalarConst(unsigned Opc) { in isScalarConst() argument
316 switch (Opc) { in isScalarConst()
331 inline bool isArgument(unsigned Opc) { in isArgument() argument
332 switch (Opc) { in isArgument()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp66 bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const { in canPerformCSEForOpc()
68 if (!CSEInfo || !CSEInfo->shouldCSE(Opc)) in canPerformCSEForOpc()
106 unsigned Opc) const { in profileMBBOpcode()
110 B.addNodeIDOpcode(Opc); in profileMBBOpcode()
113 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything() argument
118 profileMBBOpcode(B, Opc); in profileEverything()
175 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() argument
179 switch (Opc) { in buildInstr()
219 if (Opc == TargetOpcode::G_PTR_ADD && in buildInstr()
226 Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI()); in buildInstr()
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H A DCSEInfo.cpp37 bool CSEConfigFull::shouldCSEOpc(unsigned Opc) { in shouldCSEOpc() argument
38 switch (Opc) { in shouldCSEOpc()
73 bool CSEConfigConstantOnly::shouldCSEOpc(unsigned Opc) { in shouldCSEOpc() argument
74 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT || in shouldCSEOpc()
75 Opc == TargetOpcode::G_IMPLICIT_DEF; in shouldCSEOpc()
172 void GISelCSEInfo::countOpcodeHit(unsigned Opc) { in countOpcodeHit() argument
174 if (OpcodeHitTable.count(Opc)) in countOpcodeHit()
175 OpcodeHitTable[Opc] += 1; in countOpcodeHit()
177 OpcodeHitTable[Opc] in countOpcodeHit()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp393 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in materializeLoadStoreOperands() local
395 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), Reg) in materializeLoadStoreOperands()
613 unsigned Opc = in fastMaterializeAlloca() local
615 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
632 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in fastMaterializeConstant() local
634 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastMaterializeConstant()
670 unsigned Opc; in fastLowerArguments() local
677 Opc = WebAssembly::ARGUMENT_i32; in fastLowerArguments()
681 Opc = WebAssembly::ARGUMENT_i64; in fastLowerArguments()
685 Opc = WebAssembly::ARGUMENT_f32; in fastLowerArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CompressEVEX.cpp119 unsigned Opc = MI.getOpcode(); in performCustomAdjustments() local
120 switch (Opc) { in performCustomAdjustments()
128 (Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4; in performCustomAdjustments()
188 auto IsRedundantNewDataDest = [&](unsigned &Opc) { in CompressEVEXImpl() argument
208 Opc = MI.getOpcode(); in CompressEVEXImpl()
225 unsigned Opc = MI.getOpcode(); in CompressEVEXImpl() local
227 bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr; in CompressEVEXImpl()
228 bool IsRedundantNDD = IsNDLike ? IsRedundantNewDataDest(Opc) : false; in CompressEVEXImpl()
230 auto GetCompressedOpc = [&](unsigned Opc) -> unsigned { in CompressEVEXImpl() argument
232 const auto I = llvm::lower_bound(Table, Opc); in CompressEVEXImpl()
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H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
120 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
333 unsigned Opc = 0; in X86FastEmitLoad() local
337 Opc = X86::MOV8rm; in X86FastEmitLoad()
340 Opc = X86::MOV16rm; in X86FastEmitLoad()
343 Opc = X86::MOV32rm; in X86FastEmitLoad()
347 Opc = X86::MOV64rm; in X86FastEmitLoad()
350 Opc = HasAVX512 ? X86::VMOVSSZrm_alt in X86FastEmitLoad()
356 Opc = HasAVX512 ? X86::VMOVSDZrm_alt in X86FastEmitLoad()
366 Opc = HasVLX ? X86::VMOVNTDQAZ128rm : in X86FastEmitLoad()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstantFolder.h43 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp() argument
48 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldBinOp()
49 return ConstantExpr::get(Opc, LC, RC); in FoldBinOp()
50 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldBinOp()
55 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp() argument
60 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldExactBinOp()
61 return ConstantExpr::get(Opc, LC, RC, in FoldExactBinOp()
63 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldExactBinOp()
68 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp() argument
73 if (ConstantExpr::isDesirableBinOp(Opc)) { in FoldNoWrapBinOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp281 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) { in getMIMGBaseOpcode() argument
282 const MIMGInfo *Info = getMIMGInfo(Opc); in getMIMGBaseOpcode()
286 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) { in getMaskedMIMGOp() argument
287 const MIMGInfo *OrigInfo = getMIMGInfo(Opc); in getMaskedMIMGOp()
422 int getMTBUFBaseOpcode(unsigned Opc) { in getMTBUFBaseOpcode() argument
423 const MTBUFInfo *Info = getMTBUFInfoFromOpcode(Opc); in getMTBUFBaseOpcode()
432 int getMTBUFElements(unsigned Opc) { in getMTBUFElements() argument
433 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc); in getMTBUFElements()
437 bool getMTBUFHasVAddr(unsigned Opc) { in getMTBUFHasVAddr() argument
438 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc); in getMTBUFHasVAddr()
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H A DAMDGPUBaseInfo.h411 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
485 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
502 const MIMGInfo *getMIMGInfo(unsigned Opc);
505 int getMTBUFBaseOpcode(unsigned Opc);
511 int getMTBUFElements(unsigned Opc);
514 bool getMTBUFHasVAddr(unsigned Opc);
517 bool getMTBUFHasSrsrc(unsigned Opc);
520 bool getMTBUFHasSoffset(unsigned Opc);
523 int getMUBUFBaseOpcode(unsigned Opc);
529 int getMUBUFElements(unsigned Opc);
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp161 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } in isUncondBranchOpcode() argument
163 static bool isI32CondBranchOpcode(int Opc) { in isI32CondBranchOpcode() argument
164 return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA || in isI32CondBranchOpcode()
165 Opc == SP::BPICCNT || Opc == SP::BPICCANT; in isI32CondBranchOpcode()
168 static bool isI64CondBranchOpcode(int Opc) { in isI64CondBranchOpcode() argument
169 return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT || in isI64CondBranchOpcode()
170 Opc == SP::BPXCCANT; in isI64CondBranchOpcode()
173 static bool isRegCondBranchOpcode(int Opc) { in isRegCondBranchOpcode() argument
174 return Opc == SP::BPR || Opc == SP::BPRA || Opc == SP::BPRNT || in isRegCondBranchOpcode()
175 Opc == SP::BPRANT; in isRegCondBranchOpcode()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetFolder.h54 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp() argument
59 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldBinOp()
60 return Fold(ConstantExpr::get(Opc, LC, RC)); in FoldBinOp()
61 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldBinOp()
66 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp() argument
71 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldExactBinOp()
73 Opc, LC, RC, IsExact ? PossiblyExactOperator::IsExact : 0)); in FoldExactBinOp()
74 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldExactBinOp()
79 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp() argument
84 if (ConstantExpr::isDesirableBinOp(Opc)) { in FoldNoWrapBinOp()
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H A DInstSimplifyFolder.h50 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp() argument
52 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldBinOp()
55 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp() argument
57 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldExactBinOp()
60 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp() argument
62 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldNoWrapBinOp()
65 Value *FoldBinOpFMF(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldBinOpFMF() argument
67 return simplifyBinOp(Opc, LHS, RHS, FMF, SQ); in FoldBinOpFMF()
70 Value *FoldUnOpFMF(Instruction::UnaryOps Opc, Value *V, in FoldUnOpFMF() argument
72 return simplifyUnOp(Opc, V, FMF, SQ); in FoldUnOpFMF()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DWebAssemblyDisassemblerEmitter.cpp41 unsigned Opc = static_cast<unsigned>( in emitWebAssemblyDisassemblerTables() local
44 if (Opc == 0xFFFFFFFF) in emitWebAssemblyDisassemblerTables()
46 assert(Opc <= 0xFFFFFF); in emitWebAssemblyDisassemblerTables()
48 if (Opc <= 0xFFFF) { in emitWebAssemblyDisassemblerTables()
49 Prefix = Opc >> 8; in emitWebAssemblyDisassemblerTables()
50 Opc = Opc & 0xFF; in emitWebAssemblyDisassemblerTables()
52 Prefix = Opc >> 16; in emitWebAssemblyDisassemblerTables()
53 Opc = Opc & 0xFFFF; in emitWebAssemblyDisassemblerTables()
55 auto &CGIP = OpcodeTable[Prefix][Opc]; in emitWebAssemblyDisassemblerTables()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp111 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
451 unsigned Opc; in PPCEmitLoad() local
476 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; in PPCEmitLoad()
479 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
483 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
485 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) in PPCEmitLoad()
489 Opc = PPC::LD; in PPCEmitLoad()
495 Opc = Subtarget->hasSPE() ? PPC::SPELWZ : PPC::LFS; in PPCEmitLoad()
498 Opc = FP64LoadOpc; in PPCEmitLoad()
511 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; in PPCEmitLoad()
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H A DPPCCTRLoopsVerify.cpp115 unsigned Opc = I->getOpcode(); in verifyCTRBranch() local
116 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) { in verifyCTRBranch()
173 unsigned Opc = MII->getOpcode(); in runOnMachineFunction() local
174 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ || in runOnMachineFunction()
175 Opc == PPC::BDZ8 || Opc == PPC::BDZ) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp136 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue() local
138 Opc = ARC::SUB_rru6; in emitPrologue()
140 Opc = ARC::SUB_rrs12; in emitPrologue()
141 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
253 unsigned Opc = ARC::SUB_rrlimm; in emitEpilogue() local
255 Opc = ARC::SUB_rru6; in emitEpilogue()
256 BuildMI(MBB, MBBI, DebugLoc(), TII->get(Opc), ARC::SP) in emitEpilogue()
281 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
283 Opc = ARC::ADD_rru6; in emitEpilogue()
285 Opc = ARC::ADD_rrs12; in emitEpilogue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp210 static unsigned getBranchDisplacementBits(unsigned Opc) { in getBranchDisplacementBits() argument
211 switch (Opc) { in getBranchDisplacementBits()
642 unsigned Opc = 0; in canFoldIntoCSel() local
660 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
670 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
689 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
695 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
699 return Opc; in canFoldIntoCSel()
835 unsigned Opc = 0; in insertSelect() local
840 Opc = AArch64::CSELXr; in insertSelect()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp213 bool selectVectorLoadIntrinsic(unsigned Opc, unsigned NumVecs,
215 bool selectVectorLoadLaneIntrinsic(unsigned Opc, unsigned NumVecs,
218 unsigned Opc);
220 unsigned Opc);
1189 unsigned Opc = Is32Bit ? AArch64::FCSELSrrr : AArch64::FCSELDrrr; in emitSelect() local
1190 auto FCSel = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1196 unsigned Opc = Is32Bit ? AArch64::CSELWr : AArch64::CSELXr; in emitSelect() local
1198 auto TryFoldBinOpIntoSelect = [&Opc, Is32Bit, &CC, &MRI, in emitSelect()
1213 Opc = Is32Bit ? AArch64::CSNEGWr : AArch64::CSNEGXr; in emitSelect()
1230 Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr; in emitSelect()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DXRayInstrumentation.cpp96 unsigned Opc = 0; in replaceRetWithPatchableRet() local
101 Opc = TargetOpcode::PATCHABLE_RET; in replaceRetWithPatchableRet()
106 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in replaceRetWithPatchableRet()
108 if (Opc != 0) { in replaceRetWithPatchableRet()
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) in replaceRetWithPatchableRet()
129 unsigned Opc = 0; in prependRetWithPatchableExit() local
132 Opc = TargetOpcode::PATCHABLE_FUNCTION_EXIT; in prependRetWithPatchableExit()
135 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in prependRetWithPatchableExit()
137 if (Opc != 0) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.h30 unsigned Opc; variable
34 Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) { in Inst() argument
38 unsigned getOpcode() const { return Opc; } in getOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp118 unsigned getPredForm(unsigned Opc);
120 bool isScalarCmp(unsigned Opc);
144 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm() argument
147 switch (Opc) { in getPredForm()
189 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
190 if (getPredForm(Opc) != 0) in isConvertibleToPredForm()
197 switch (Opc) { in isConvertibleToPredForm()
210 unsigned Opc = MI.getOpcode(); in collectPredicateGPR() local
211 switch (Opc) { in collectPredicateGPR()
256 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
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