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Searched refs:Opc (Results 1 – 25 of 395) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp44 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
46 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
47 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
66 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
68 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
69 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
85 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
91 Opc = Mips::MOVE16_MM; in copyPhysReg()
93 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
95 Opc = Mips::CFC1; in copyPhysReg()
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H A DMips16InstrInfo.cpp71 unsigned Opc = 0; in copyPhysReg() local
75 Opc = Mips::MoveR3216; in copyPhysReg()
78 Opc = Mips::Move32R16; in copyPhysReg()
81 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
84 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
86 assert(Opc && "Cannot copy registers"); in copyPhysReg()
88 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
114 unsigned Opc = 0; in storeRegToStack() local
116 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
117 assert(Opc && "Register class not handled!"); in storeRegToStack()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h126 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
562 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
563 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
569 static inline bool isVPTOpcode(int Opc) { in isVPTOpcode() argument
570 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || in isVPTOpcode()
571 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || in isVPTOpcode()
572 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || in isVPTOpcode()
573 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || in isVPTOpcode()
574 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || in isVPTOpcode()
575 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || in isVPTOpcode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.h147 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { in GetDefaultP2AlignAny() argument
148 switch (Opc) { in GetDefaultP2AlignAny()
278 inline unsigned GetDefaultP2Align(unsigned Opc) { in GetDefaultP2Align() argument
279 auto Align = GetDefaultP2AlignAny(Opc); in GetDefaultP2Align()
286 inline bool isConst(unsigned Opc) { in isConst() argument
287 switch (Opc) { in isConst()
314 inline bool isScalarConst(unsigned Opc) { in isScalarConst() argument
315 switch (Opc) { in isScalarConst()
330 inline bool isArgument(unsigned Opc) { in isArgument() argument
331 switch (Opc) { in isArgument()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp64 bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const { in canPerformCSEForOpc()
66 if (!CSEInfo || !CSEInfo->shouldCSE(Opc)) in canPerformCSEForOpc()
110 unsigned Opc) const { in profileMBBOpcode()
114 B.addNodeIDOpcode(Opc); in profileMBBOpcode()
117 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything() argument
122 profileMBBOpcode(B, Opc); in profileEverything()
179 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() argument
183 switch (Opc) { in buildInstr()
225 if (Opc == TargetOpcode::G_PTR_ADD && in buildInstr()
232 Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI()); in buildInstr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp308 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) { in getMIMGBaseOpcode() argument
309 const MIMGInfo *Info = getMIMGInfo(Opc); in getMIMGBaseOpcode()
313 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) { in getMaskedMIMGOp() argument
314 const MIMGInfo *OrigInfo = getMIMGInfo(Opc); in getMaskedMIMGOp()
463 int getMTBUFBaseOpcode(unsigned Opc) { in getMTBUFBaseOpcode() argument
464 const MTBUFInfo *Info = getMTBUFInfoFromOpcode(Opc); in getMTBUFBaseOpcode()
474 int getMTBUFElements(unsigned Opc) { in getMTBUFElements() argument
475 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc); in getMTBUFElements()
479 bool getMTBUFHasVAddr(unsigned Opc) { in getMTBUFHasVAddr() argument
480 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc); in getMTBUFHasVAddr()
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H A DAMDGPUBaseInfo.h436 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
510 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
527 const MIMGInfo *getMIMGInfo(unsigned Opc);
530 int getMTBUFBaseOpcode(unsigned Opc);
536 int getMTBUFElements(unsigned Opc);
539 bool getMTBUFHasVAddr(unsigned Opc);
542 bool getMTBUFHasSrsrc(unsigned Opc);
545 bool getMTBUFHasSoffset(unsigned Opc);
548 int getMUBUFBaseOpcode(unsigned Opc);
554 int getMUBUFElements(unsigned Opc);
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp399 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in materializeLoadStoreOperands() local
401 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), Reg) in materializeLoadStoreOperands()
619 unsigned Opc = in fastMaterializeAlloca() local
621 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
638 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in fastMaterializeConstant() local
640 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastMaterializeConstant()
676 unsigned Opc; in fastLowerArguments() local
683 Opc = WebAssembly::ARGUMENT_i32; in fastLowerArguments()
687 Opc = WebAssembly::ARGUMENT_i64; in fastLowerArguments()
691 Opc = WebAssembly::ARGUMENT_f32; in fastLowerArguments()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DWebAssemblyDisassemblerEmitter.cpp39 unsigned Opc = static_cast<unsigned>(*Inst.convertInitializerToInt()); in emitWebAssemblyDisassemblerTables() local
40 if (Opc == 0xFFFFFFFF) in emitWebAssemblyDisassemblerTables()
42 assert(Opc <= 0xFFFFFF); in emitWebAssemblyDisassemblerTables()
44 if (Opc <= 0xFFFF) { in emitWebAssemblyDisassemblerTables()
45 Prefix = Opc >> 8; in emitWebAssemblyDisassemblerTables()
46 Opc = Opc & 0xFF; in emitWebAssemblyDisassemblerTables()
48 Prefix = Opc >> 16; in emitWebAssemblyDisassemblerTables()
49 Opc = Opc & 0xFFFF; in emitWebAssemblyDisassemblerTables()
51 auto &CGIP = OpcodeTable[Prefix][Opc]; in emitWebAssemblyDisassemblerTables()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstantFolder.h44 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp() argument
49 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldBinOp()
50 return ConstantExpr::get(Opc, LC, RC); in FoldBinOp()
51 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldBinOp()
56 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp() argument
61 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldExactBinOp()
62 return ConstantExpr::get(Opc, LC, RC, in FoldExactBinOp()
64 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldExactBinOp()
69 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp() argument
74 if (ConstantExpr::isDesirableBinOp(Opc)) { in FoldNoWrapBinOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CompressEVEX.cpp119 unsigned Opc = MI.getOpcode(); in performCustomAdjustments() local
120 switch (Opc) { in performCustomAdjustments()
128 (Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4; in performCustomAdjustments()
188 auto IsRedundantNewDataDest = [&](unsigned &Opc) { in CompressEVEXImpl() argument
208 Opc = MI.getOpcode(); in CompressEVEXImpl()
225 unsigned Opc = MI.getOpcode(); in CompressEVEXImpl() local
227 bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr; in CompressEVEXImpl()
228 bool IsRedundantNDD = IsNDLike ? IsRedundantNewDataDest(Opc) : false; in CompressEVEXImpl()
230 auto GetCompressedOpc = [&](unsigned Opc) -> unsigned { in CompressEVEXImpl() argument
232 const auto I = llvm::lower_bound(Table, Opc); in CompressEVEXImpl()
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H A DX86ExpandPseudo.cpp198 unsigned Opc = -1; in expandCALL_RVMARKER() local
200 Opc = X86::CALL64m; in expandCALL_RVMARKER()
202 Opc = X86::CALL64r; in expandCALL_RVMARKER()
204 Opc = X86::CALL64pcrel32; in expandCALL_RVMARKER()
208 OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr(); in expandCALL_RVMARKER()
591 unsigned Opc; in expandMI() local
594 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDRS); in expandMI()
597 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDRST1); in expandMI()
600 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADD); in expandMI()
603 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDT1); in expandMI()
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H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, Register Src, EVT SrcVT,
120 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
334 unsigned Opc = 0; in X86FastEmitLoad() local
338 Opc = X86::MOV8rm; in X86FastEmitLoad()
341 Opc = X86::MOV16rm; in X86FastEmitLoad()
344 Opc = X86::MOV32rm; in X86FastEmitLoad()
348 Opc = X86::MOV64rm; in X86FastEmitLoad()
351 Opc = HasAVX512 ? X86::VMOVSSZrm_alt in X86FastEmitLoad()
357 Opc = HasAVX512 ? X86::VMOVSDZrm_alt in X86FastEmitLoad()
367 Opc = HasVLX ? X86::VMOVNTDQAZ128rm : in X86FastEmitLoad()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp159 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } in isUncondBranchOpcode() argument
161 static bool isI32CondBranchOpcode(int Opc) { in isI32CondBranchOpcode() argument
162 return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA || in isI32CondBranchOpcode()
163 Opc == SP::BPICCNT || Opc == SP::BPICCANT; in isI32CondBranchOpcode()
166 static bool isI64CondBranchOpcode(int Opc) { in isI64CondBranchOpcode() argument
167 return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT || in isI64CondBranchOpcode()
168 Opc == SP::BPXCCANT; in isI64CondBranchOpcode()
171 static bool isRegCondBranchOpcode(int Opc) { in isRegCondBranchOpcode() argument
172 return Opc == SP::BPR || Opc == SP::BPRA || Opc == SP::BPRNT || in isRegCondBranchOpcode()
173 Opc == SP::BPRANT; in isRegCondBranchOpcode()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetFolder.h55 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp() argument
60 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldBinOp()
61 return Fold(ConstantExpr::get(Opc, LC, RC)); in FoldBinOp()
62 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldBinOp()
67 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp() argument
72 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldExactBinOp()
74 Opc, LC, RC, IsExact ? PossiblyExactOperator::IsExact : 0)); in FoldExactBinOp()
75 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldExactBinOp()
80 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp() argument
85 if (ConstantExpr::isDesirableBinOp(Opc)) { in FoldNoWrapBinOp()
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H A DInstSimplifyFolder.h52 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp() argument
54 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldBinOp()
57 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp() argument
59 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldExactBinOp()
62 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp() argument
64 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldNoWrapBinOp()
67 Value *FoldBinOpFMF(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldBinOpFMF() argument
69 return simplifyBinOp(Opc, LHS, RHS, FMF, SQ); in FoldBinOpFMF()
72 Value *FoldUnOpFMF(Instruction::UnaryOps Opc, Value *V, in FoldUnOpFMF() argument
74 return simplifyUnOp(Opc, V, FMF, SQ); in FoldUnOpFMF()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp106 Register fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
439 unsigned Opc; in PPCEmitLoad() local
464 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; in PPCEmitLoad()
467 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
471 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
473 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) in PPCEmitLoad()
477 Opc = PPC::LD; in PPCEmitLoad()
483 Opc = Subtarget->hasSPE() ? PPC::SPELWZ : PPC::LFS; in PPCEmitLoad()
486 Opc = FP64LoadOpc; in PPCEmitLoad()
499 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; in PPCEmitLoad()
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H A DPPCCTRLoopsVerify.cpp113 unsigned Opc = I->getOpcode(); in verifyCTRBranch() local
114 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) { in verifyCTRBranch()
171 unsigned Opc = MII->getOpcode(); in runOnMachineFunction() local
172 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ || in runOnMachineFunction()
173 Opc == PPC::BDZ8 || Opc == PPC::BDZ) in runOnMachineFunction()
H A DPPCReduceCRLogicals.cpp398 unsigned Opc = MI.getOpcode(); in isCRLogical() local
399 return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR || in isCRLogical()
400 Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CRNOT || in isCRLogical()
401 Opc == PPC::CREQV || Opc == PPC::CRANDC || Opc == PPC::CRORC || in isCRLogical()
402 Opc == PPC::CRSET || Opc == PPC::CRUNSET || Opc == PPC::CR6SET || in isCRLogical()
403 Opc == PPC::CR6UNSET; in isCRLogical()
509 unsigned Opc = UseMI.getOpcode(); in createCRLogicalOpInfo() local
510 if (Opc == PPC::ISEL || Opc == PPC::ISEL8) in createCRLogicalOpInfo()
512 if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR || in createCRLogicalOpInfo()
513 Opc == PPC::BCLRn) in createCRLogicalOpInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp136 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue() local
138 Opc = ARC::SUB_rru6; in emitPrologue()
140 Opc = ARC::SUB_rrs12; in emitPrologue()
141 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
253 unsigned Opc = ARC::SUB_rrlimm; in emitEpilogue() local
255 Opc = ARC::SUB_rru6; in emitEpilogue()
256 BuildMI(MBB, MBBI, DebugLoc(), TII->get(Opc), ARC::SP) in emitEpilogue()
281 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
283 Opc = ARC::ADD_rru6; in emitEpilogue()
285 Opc = ARC::ADD_rrs12; in emitEpilogue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp213 bool selectVectorLoadIntrinsic(unsigned Opc, unsigned NumVecs,
215 bool selectVectorLoadLaneIntrinsic(unsigned Opc, unsigned NumVecs,
218 unsigned Opc);
220 unsigned Opc);
1197 unsigned Opc = Is32Bit ? AArch64::FCSELSrrr : AArch64::FCSELDrrr; in emitSelect() local
1198 auto FCSel = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1204 unsigned Opc = Is32Bit ? AArch64::CSELWr : AArch64::CSELXr; in emitSelect() local
1206 auto TryFoldBinOpIntoSelect = [&Opc, Is32Bit, &CC, &MRI, in emitSelect()
1221 Opc = Is32Bit ? AArch64::CSNEGWr : AArch64::CSNEGXr; in emitSelect()
1238 Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr; in emitSelect()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp240 static unsigned getBranchDisplacementBits(unsigned Opc) { in getBranchDisplacementBits() argument
241 switch (Opc) { in getBranchDisplacementBits()
702 unsigned Opc = 0; in canFoldIntoCSel() local
720 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
730 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
749 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
755 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
759 return Opc; in canFoldIntoCSel()
937 unsigned Opc = 0; in insertSelect() local
942 Opc = AArch64::CSELXr; in insertSelect()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.h30 unsigned Opc; variable
34 Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) { in Inst() argument
38 unsigned getOpcode() const { return Opc; } in getOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp93 unsigned getPredForm(unsigned Opc);
95 bool isScalarCmp(unsigned Opc);
119 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm() argument
122 switch (Opc) { in getPredForm()
164 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
165 if (getPredForm(Opc) != 0) in isConvertibleToPredForm()
172 switch (Opc) { in isConvertibleToPredForm()
185 unsigned Opc = MI.getOpcode(); in collectPredicateGPR() local
186 switch (Opc) { in collectPredicateGPR()
233 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp170 unsigned Opc = MI.getOpcode(); in printWWMInfo() local
172 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::ENTER_STRICT_WQM) { in printWWMInfo()
175 assert(Opc == AMDGPU::EXIT_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WQM); in printWWMInfo()
179 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WWM) { in printWWMInfo()
182 assert(Opc == AMDGPU::ENTER_STRICT_WQM || Opc == AMDGPU::EXIT_STRICT_WQM); in printWWMInfo()

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