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Searched refs:OpSizeInBits (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanTransforms.cpp1178 unsigned OpSizeInBits = in truncateToMinimalBitwidths() local
1180 if (OpSizeInBits == NewResSizeInBits) in truncateToMinimalBitwidths()
1182 assert(OpSizeInBits > NewResSizeInBits && "nothing to truncate"); in truncateToMinimalBitwidths()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp7442 unsigned OpSizeInBits = VT.getSizeInBits(); in MatchBSwapHWordLow() local
7443 if (OpSizeInBits > 16) { in MatchBSwapHWordLow()
7455 unsigned HighBit = DemandHighBits ? OpSizeInBits : 24; in MatchBSwapHWordLow()
7457 APInt::getBitsSet(OpSizeInBits, 16, HighBit))) in MatchBSwapHWordLow()
7463 if (OpSizeInBits > 16) { in MatchBSwapHWordLow()
7466 DAG.getShiftAmountConstant(OpSizeInBits - 16, VT, DL)); in MatchBSwapHWordLow()
9870 unsigned OpSizeInBits = VT.getScalarSizeInBits(); in visitSHL() local
9905 if (DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits))) in visitSHL()
9917 auto MatchOutOfRange = [OpSizeInBits](ConstantSDNode *LHS, in visitSHL()
9922 return (c1 + c2).uge(OpSizeInBits); in visitSHL()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp17768 unsigned OpSizeInBits = VT.getScalarSizeInBits(); in stripModuloOnShift() local
17789 if (Mask->getZExtValue() == OpSizeInBits - 1) in stripModuloOnShift()