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Searched refs:OpSel (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp379 int64_t OpSel = 0; in createDPPInst() local
380 OpSel |= (Mod0 ? (!!(Mod0->getImm() & SISrcMods::OP_SEL_0) << 0) : 0); in createDPPInst()
381 OpSel |= (Mod1 ? (!!(Mod1->getImm() & SISrcMods::OP_SEL_0) << 1) : 0); in createDPPInst()
382 OpSel |= (Mod2 ? (!!(Mod2->getImm() & SISrcMods::OP_SEL_0) << 2) : 0); in createDPPInst()
384 OpSel |= !!(Mod0->getImm() & SISrcMods::DST_OP_SEL) << 3; in createDPPInst()
386 if (OpSel != 0) { in createDPPInst()
392 DPPInst.addImm(OpSel); in createDPPInst()
H A DSIPeepholeSDWA.cpp527 AMDGPU::OpName SrcSelOpName, SdwaSel OpSel) { in canCombineOpSel() argument
533 return combineSdwaSel(SrcSel, OpSel).has_value(); in canCombineOpSel()
542 SdwaSel OpSel) { in canCombineOpSel() argument
549 return canCombineOpSel(MI, TII, SrcSelOpName, OpSel); in canCombineOpSel()
H A DAMDGPUISelDAGToDAG.h213 bool OpSel) const;
H A DAMDGPUInstructionSelector.h163 bool OpSel = false) const;
H A DSIDefines.h1008 enum OpSel : uint64_t { enum
H A DVOPInstructions.td269 // 16-bit select fields which can be interpreted as OpSel or hi/lo suffix
886 // 16-bit select fields which can be interpreted as OpSel or hi/lo suffix
1470 class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> {
1472 bit HasOpSel = OpSel;
H A DVOPCInstructions.td93 let HasModifiers = 1; // All instructions at least have OpSel
167 let HasModifiers = 1; // All instructions at least have OpSel
910 let HasModifiers = 1; // All instructions at least have OpSel
981 let HasModifiers = 1; // All instructions at least have OpSel
H A DAMDGPUISelDAGToDAG.cpp3089 bool OpSel) const { in SelectVINTERPModsImpl()
3094 if (OpSel) in SelectVINTERPModsImpl()
H A DSIInstrInfo.td1245 def op_sel0 : ArrayOperand0<"op_sel", "OpSel">;
2792 let HasModifiers = 1; // All instructions at least have OpSel.
H A DSIInstrInfo.cpp4092 const MachineOperand *OpSel = getNamedOperand(MI, AMDGPU::OpName::op_sel); in convertToThreeAddress() local
4216 MIB.addImm(OpSel ? OpSel->getImm() : 0); in convertToThreeAddress()
H A DAMDGPUInstructionSelector.cpp4171 Register Src, bool IsCanonicalizing, bool AllowAbs, bool OpSel) const { in selectVOP3ModsImpl()
4195 if (OpSel) in selectVOP3ModsImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1019 unsigned OpSel = 0; member
1042 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; in collectVOPModifiers()
1048 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; in collectVOPModifiers()
1132 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), in convertDPP8Inst()
1161 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), in convertVOP3DPPInst()
1330 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), in convertVOP3PDPPInst()
1375 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), in convertVOPC64DPPInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4857 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm(); in validateOpSel() local
4859 if (OpSel & ~3) in validateOpSel()
4882 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm(); in validateOpSel() local
4883 if (OpSel & 3) in validateOpSel()
8965 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm(); in cvtVOP3DstOpSelOnly() local
8979 if ((OpSel & (1 << SrcNum)) != 0) in cvtVOP3DstOpSelOnly()
9087 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm(); in cvtVINTERP() local
9097 if ((OpSel & (1 << J)) != 0) in cvtVINTERP()
9100 (OpSel & (1 << 3)) != 0) in cvtVINTERP()
9157 unsigned OpSel = 0; in cvtScaledMFMA() local
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