| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | BreakFalseDeps.cpp | 136 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
138 assert(OpRC && "Not a valid register class"); in pickBestRegisterForUndef()
143 if (CurrMO.isUndef() || !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
155 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| H A D | MachineInstr.cpp | 1041 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
1047 if (OpRC) in getRegClassConstraintEffect()
1048 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
1051 } else if (OpRC) in getRegClassConstraintEffect()
1052 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
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| H A D | RegAllocFast.cpp | 1339 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts() local
1344 if (OpRC->hasSubClassEq(IdxRC)) in addRegClassDefCounts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 1650 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
1651 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1655 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
1656 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
1658 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1672 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1692 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1693 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1694 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1696 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 336 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
338 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
340 if (OpRC) { in AddRegisterOperand()
349 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
351 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
352 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
353 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
414 const TargetRegisterClass *OpRC = in AddOperand() local
421 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) { in AddOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 932 const TargetRegisterClass *OpRC = getRegOpRC(*MRI, *TRI, SrcOp); in getRegSeqInit() local
934 RC = OpRC; in getRegSeqInit()
935 else if (!TRI->getCommonSubClass(RC, OpRC)) in getRegSeqInit()
1052 const TargetRegisterClass *OpRC = TRI->getRegClass(RCID); in tryFoldRegSeqSplat() local
1065 OpRC = TRI->getSubRegisterClass(OpRC, AMDGPU::sub0); in tryFoldRegSeqSplat()
1068 OpRC = TRI->getSubRegisterClass(OpRC, AMDGPU::sub0_sub1); in tryFoldRegSeqSplat()
1074 if (!TRI->getCommonSubClass(OpRC, SplatRC)) in tryFoldRegSeqSplat()
2360 const TargetRegisterClass *OpRC = in tryFoldRegSequence() local
2362 if (!OpRC || !TRI->isVectorSuperClass(OpRC)) in tryFoldRegSequence()
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| H A D | SIInstrInfo.cpp | 6531 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
6535 if (DstRC == OpRC) in legalizeGenericOperand()
6900 const TargetRegisterClass *OpRC = in legalizeOperands() local
6902 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
6903 VRC = OpRC; in legalizeOperands()
6905 SRC = OpRC; in legalizeOperands()
6962 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
6963 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
6964 if (VRC == OpRC) in legalizeOperands()
9009 const TargetRegisterClass *OpRC = in findUsedSGPR() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 117 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
123 if (OpRC) { in constrainOperandRegClass()
129 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI))) in constrainOperandRegClass()
130 OpRC = SubRC; in constrainOperandRegClass()
132 OpRC = TRI.getAllocatableClass(OpRC); in constrainOperandRegClass()
135 if (!OpRC) { in constrainOperandRegClass()
151 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1889 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1891 return OpRC->hasSubClassEq(RRC); in validateReg()
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