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Searched refs:OpRC (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DBreakFalseDeps.cpp137 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
139 assert(OpRC && "Not a valid register class"); in pickBestRegisterForUndef()
144 if (CurrMO.isUndef() || !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
H A DMachineInstr.cpp1014 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
1020 if (OpRC) in getRegClassConstraintEffect()
1021 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
1024 } else if (OpRC) in getRegClassConstraintEffect()
1025 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
H A DRegAllocFast.cpp1273 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts() local
1278 if (OpRC->hasSubClassEq(IdxRC)) in addRegClassDefCounts()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1653 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
1654 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1658 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
1659 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
1661 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1675 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1695 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1696 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1697 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1699 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp338 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
340 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
342 if (OpRC) { in AddRegisterOperand()
351 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
353 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
354 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
355 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
417 const TargetRegisterClass *OpRC = in AddOperand() local
424 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) { in AddOperand()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp117 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
123 if (OpRC) { in constrainOperandRegClass()
129 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI))) in constrainOperandRegClass()
130 OpRC = SubRC; in constrainOperandRegClass()
132 OpRC = TRI.getAllocatableClass(OpRC); in constrainOperandRegClass()
135 if (!OpRC) { in constrainOperandRegClass()
151 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1814 const TargetRegisterClass *OpRC = in tryFoldRegSequence() local
1816 if (!OpRC || !TRI->isVectorSuperClass(OpRC)) in tryFoldRegSequence()
H A DSIInstrInfo.cpp6226 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
6230 if (DstRC == OpRC) in legalizeGenericOperand()
6592 const TargetRegisterClass *OpRC = in legalizeOperands() local
6594 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
6595 VRC = OpRC; in legalizeOperands()
6597 SRC = OpRC; in legalizeOperands()
6654 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
6655 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
6656 if (VRC == OpRC) in legalizeOperands()
8523 const TargetRegisterClass *OpRC = in findUsedSGPR() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp1911 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1913 return OpRC->hasSubClassEq(RRC); in validateReg()