Searched refs:OpOpcode (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeInfo.cpp | 121 unsigned OpOpcode = N->getOperand(OpIdx).getOpcode(); in verifyNode() local 122 if (OpOpcode != ISD::Register && OpOpcode != ISD::RegisterMask) in verifyNode()
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| H A D | SelectionDAG.cpp | 6347 unsigned OpOpcode = N1.getNode()->getOpcode(); in getNode() local 6352 assert(OpOpcode == ISD::TargetConstant && in getNode() 6407 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) { in getNode() 6409 if (OpOpcode == ISD::ZERO_EXTEND) in getNode() 6411 SDValue NewVal = getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags); in getNode() 6416 if (OpOpcode == ISD::POISON) in getNode() 6434 if (OpOpcode == ISD::ZERO_EXTEND) { // (zext (zext x)) -> (zext x) in getNode() 6443 if (OpOpcode == ISD::POISON) in getNode() 6454 if (OpOpcode == ISD::TRUNCATE) { in getNode() 6480 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3687 unsigned OpOpcode = Op.getOpcode(); in LowerFP_TO_INT() local 3705 SDValue FpToInt32 = DAG.getNode(OpOpcode, DL, MVT::i32, Src); in LowerFP_TO_INT() 3716 SDValue FpToInt32 = DAG.getNode(OpOpcode, DL, MVT::i32, Src); in LowerFP_TO_INT() 3718 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT() 3723 return LowerFP_TO_INT64(Op, DAG, OpOpcode == ISD::FP_TO_SINT); in LowerFP_TO_INT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 17116 unsigned OpOpcode = Op.getNode()->getOpcode(); in PerformVMulVCTPCombine() local 17118 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) in PerformVMulVCTPCombine() 17155 bool isSigned = OpOpcode == ISD::SINT_TO_FP; in PerformVMulVCTPCombine()
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