| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 67 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
148 bool AVRExpandPseudo::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, in expandArith() argument
161 buildMI(MBB, MBBI, OpLo) in expandArith()
366 unsigned OpLo = AVR::SBCIRdK; in expand() local
371 buildMI(MBB, MBBI, OpLo) in expand()
428 unsigned OpLo = AVR::COMRd; in expand() local
433 buildMI(MBB, MBBI, OpLo) in expand()
500 unsigned OpLo = AVR::CPRdRr; in expand() local
506 buildMI(MBB, MBBI, OpLo) in expand()
533 unsigned OpLo = AVR::CPCRdRr; in expand() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1850 SDValue OpLo = Op; in SplitVecRes_StrictFPOp() local
1858 GetSplitVector(Op, OpLo, OpHi); in SplitVecRes_StrictFPOp()
1860 std::tie(OpLo, OpHi) = DAG.SplitVectorOperand(N, i); in SplitVecRes_StrictFPOp()
1863 OpsLo[i] = OpLo; in SplitVecRes_StrictFPOp()
3337 SDValue OpLo, OpHi; in SplitVecRes_VECTOR_DEINTERLEAVE() local
3338 GetSplitVector(N->getOperand(i), OpLo, OpHi); in SplitVecRes_VECTOR_DEINTERLEAVE()
3339 Ops[i * 2] = OpLo; in SplitVecRes_VECTOR_DEINTERLEAVE()
3360 SDValue OpLo, OpHi; in SplitVecRes_VECTOR_INTERLEAVE() local
3361 GetSplitVector(N->getOperand(i), OpLo, OpHi); in SplitVecRes_VECTOR_INTERLEAVE()
3362 Ops[i] = OpLo; in SplitVecRes_VECTOR_INTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1958 const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3); in evaluate() local
1961 RegSubRegPair SrcRL(getRegSubRegPair(OpLo)), SrcRH(getRegSubRegPair(OpHi)); in evaluate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2459 MachineOperand OpLo = MI.getOperand(1); in expandPostRAPseudo() local
2485 if (OpLo.isGlobal()) in expandPostRAPseudo()
2486 OpLo.setOffset(OpLo.getOffset() + Adjust + 4); in expandPostRAPseudo()
2488 BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo).addReg(RegLo).add(OpLo)); in expandPostRAPseudo()
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| H A D | SIISelLowering.cpp | 6038 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo, Op->getFlags()); in splitUnaryVectorOp() local
6041 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
6062 SDValue OpLo = in splitBinaryVectorOp() local
6067 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
6092 SDValue OpLo = in splitTernaryVectorOp() local
6097 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitTernaryVectorOp()
7035 SDValue OpLo = DAG.getNode(Opc, DL, HalfDstVT, Lo, Flags); in splitFP_ROUNDVectorOp() local
7038 return DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, OpLo, OpHi); in splitFP_ROUNDVectorOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11868 auto [OpLo, OpHi] = DAG.SplitVectorOperand(Op.getNode(), i); in lowerVECTOR_DEINTERLEAVE()
11869 Ops[i * 2] = OpLo; in lowerVECTOR_DEINTERLEAVE()
12060 auto [OpLo, OpHi] = DAG.SplitVectorOperand(Op.getNode(), i); in lowerVECTOR_INTERLEAVE()
12061 Ops[i] = OpLo; in lowerVECTOR_INTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 20910 SDValue OpLo = DAG.getNode(ExtendInVecOpc, dl, HalfVT, In); in LowerAVXExtend() local
20916 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpLo); in LowerAVXExtend()
20924 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); in LowerAVXExtend()
21494 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, in LowerTRUNCATE() local
21499 return DAG.getVectorShuffle(VT, DL, DAG.getBitcast(MVT::v4i32, OpLo), in LowerTRUNCATE()
25440 SDValue OpLo = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, dl, HalfVT, In); in LowerSIGN_EXTEND() local
25450 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); in LowerSIGN_EXTEND()
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