| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | PredicateExpander.h | 58 void expandCheckImmOperand(raw_ostream &OS, int OpIndex, int ImmVal,
60 void expandCheckImmOperand(raw_ostream &OS, int OpIndex, StringRef ImmVal,
62 void expandCheckImmOperandSimple(raw_ostream &OS, int OpIndex,
64 void expandCheckImmOperandLT(raw_ostream &OS, int OpIndex, int ImmVal,
66 void expandCheckImmOperandGT(raw_ostream &OS, int OpIndex, int ImmVal,
68 void expandCheckRegOperand(raw_ostream &OS, int OpIndex, const Record *Reg,
70 void expandCheckRegOperandSimple(raw_ostream &OS, int OpIndex,
81 void expandCheckIsRegOperand(raw_ostream &OS, int OpIndex);
82 void expandCheckIsVRegOperand(raw_ostream &OS, int OpIndex);
83 void expandCheckIsImmOperand(raw_ostream &OS, int OpIndex);
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| H A D | PredicateExpander.cpp | 22 void PredicateExpander::expandCheckImmOperand(raw_ostream &OS, int OpIndex, in expandCheckImmOperand() argument
27 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex in expandCheckImmOperand()
34 void PredicateExpander::expandCheckImmOperand(raw_ostream &OS, int OpIndex, in expandCheckImmOperand() argument
38 expandCheckImmOperandSimple(OS, OpIndex, FunctionMapper); in expandCheckImmOperand()
42 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex in expandCheckImmOperand()
50 int OpIndex, in expandCheckImmOperandSimple() argument
56 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex in expandCheckImmOperandSimple()
62 void PredicateExpander::expandCheckImmOperandLT(raw_ostream &OS, int OpIndex, in expandCheckImmOperandLT() argument
67 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex in expandCheckImmOperandLT()
74 void PredicateExpander::expandCheckImmOperandGT(raw_ostream &OS, int OpIndex, in expandCheckImmOperandGT() argument
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 347 Write.OpIndex = i; in populateWrites()
362 dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex in populateWrites()
374 Write.OpIndex = ~CurrentDef; in populateWrites()
392 dbgs() << "\t\t[Def][I] OpIdx=" << ~Write.OpIndex in populateWrites()
401 Write.OpIndex = OptionalDefIdx; in populateWrites()
407 dbgs() << "\t\t[Def][O] OpIdx=" << Write.OpIndex in populateWrites()
418 for (unsigned I = 0, OpIndex = MCDesc.getNumOperands(); in populateWrites() local
419 I < NumVariadicOps && !AssumeUsesOnly; ++I, ++OpIndex) { in populateWrites()
420 const MCOperand &Op = MCI.getOperand(OpIndex); in populateWrites()
427 Write.OpIndex = OpIndex; in populateWrites()
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| H A D | Instruction.cpp | 126 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID " in dump()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsELFStreamer.cpp | 43 for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) { in emitInstruction() local
44 const MCOperand &Op = Inst.getOperand(OpIndex); in emitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 576 unsigned OpIndex = Desc.NumDefs; in evaluateMemoryOperandAddress() local
577 while (OpIndex < Desc.getNumOperands() && in evaluateMemoryOperandAddress()
578 Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY) in evaluateMemoryOperandAddress()
579 ++OpIndex; in evaluateMemoryOperandAddress()
580 if (OpIndex == Desc.getNumOperands()) in evaluateMemoryOperandAddress()
608 return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr); in evaluateMemoryOperandAddress()
610 return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr); in evaluateMemoryOperandAddress()
612 return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr); in evaluateMemoryOperandAddress()
614 return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, OpIndex, Addr); in evaluateMemoryOperandAddress()
616 return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr); in evaluateMemoryOperandAddress()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 139 int OpIndex; member
159 bool isImplicitWrite() const { return OpIndex < 0; }; in isImplicitWrite()
167 int OpIndex; member
177 bool isImplicitRead() const { return OpIndex < 0; }; in isImplicitRead()
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| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFDebugLine.cpp | 501 OpIndex = 0; in reset()
519 << format(" %6u %3u %13u %7u ", File, Isa, Discriminator, OpIndex) in dump()
690 uint64_t AddrOffset = ((Row.OpIndex + OperationAdvance) / MaxOpsPerInst) * in advanceAddrOpIndex()
694 uint8_t PrevOpIndex = Row.OpIndex; in advanceAddrOpIndex()
695 Row.OpIndex = (Row.OpIndex + OperationAdvance) % MaxOpsPerInst; in advanceAddrOpIndex()
696 int16_t OpIndexDelta = static_cast<int16_t>(Row.OpIndex) - PrevOpIndex; in advanceAddrOpIndex()
956 State.Row.OpIndex = 0; in parse()
1166 State.Row.OpIndex = 0; in parse()
1238 << ", op-index += " << Delta.OpIndex; in parse()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
| H A D | DWARFDebugLine.h | 173 uint8_t OpIndex; member
404 int16_t OpIndex; member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| H A D | X86FastISel.cpp | 1923 unsigned TypeIndex, OpIndex; in X86SelectDivRem() local
1937 case Instruction::SDiv: OpIndex = 0; break; in X86SelectDivRem()
1938 case Instruction::SRem: OpIndex = 1; break; in X86SelectDivRem()
1939 case Instruction::UDiv: OpIndex = 2; break; in X86SelectDivRem()
1940 case Instruction::URem: OpIndex = 3; break; in X86SelectDivRem()
1944 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem()
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| H A D | X86ISelLowering.cpp | 16733 unsigned OpIndex = i / 2; in lowerV4X128Shuffle() local
16734 if (Ops[OpIndex].isUndef()) in lowerV4X128Shuffle()
16735 Ops[OpIndex] = Op; in lowerV4X128Shuffle()
16736 else if (Ops[OpIndex] != Op) in lowerV4X128Shuffle()
38624 unsigned OpIndex = i / 2; in combineX86ShuffleChain() local
38625 if (Ops[OpIndex].isUndef()) in combineX86ShuffleChain()
38626 Ops[OpIndex] = Op; in combineX86ShuffleChain()
38627 else if (Ops[OpIndex] != Op) in combineX86ShuffleChain()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1715 unsigned OpIndex; in selectMulDivRem() local
1720 OpIndex = 0; in selectMulDivRem()
1723 OpIndex = 1; in selectMulDivRem()
1726 OpIndex = 2; in selectMulDivRem()
1729 OpIndex = 3; in selectMulDivRem()
1732 OpIndex = 4; in selectMulDivRem()
1735 OpIndex = 5; in selectMulDivRem()
1738 OpIndex = 6; in selectMulDivRem()
1744 TypeEntry.ResultTable[OpIndex]; in selectMulDivRem()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | AsmWriterEmitter.cpp | 773 int OpIndex, PrintIndex; in formatAliasString() local
774 std::tie(OpIndex, PrintIndex) = getOpData(Name); in formatAliasString()
777 OS << format("\\x%02X", (unsigned char)OpIndex + 1); in formatAliasString()
782 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); in formatAliasString()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TypeBasedAliasAnalysis.cpp | 298 unsigned OpIndex = FirstFieldOpNo + FieldIndex * NumOpsPerField; in getFieldType() local
299 auto *TypeNode = cast<MDNode>(getNode()->getOperand(OpIndex)); in getFieldType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVModuleAnalysis.cpp | 64 static unsigned getMetadataUInt(MDNode *MdNode, unsigned OpIndex, in getMetadataUInt() argument
66 if (MdNode && OpIndex < MdNode->getNumOperands()) { in getMetadataUInt()
67 const auto &Op = MdNode->getOperand(OpIndex); in getMetadataUInt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 470 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); in getSingleInstruction() local
471 MCOperand &MCO = MI.getOperand(OpIndex); in getSingleInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 4771 int OpIndex; in orderFrameObjects() local
4775 OpIndex = 3; in orderFrameObjects()
4781 OpIndex = 1; in orderFrameObjects()
4784 OpIndex = -1; in orderFrameObjects()
4788 if (OpIndex >= 0) { in orderFrameObjects()
4789 const MachineOperand &MO = MI.getOperand(OpIndex); in orderFrameObjects()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetInstrPredicate.td | 92 int OpIndex = Index;
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 301 unsigned OpIndex = any_of(Shuf->getShuffleMask(), [&NumOpElts](int M) { in widenSubvectorLoad() local
305 auto *Load = dyn_cast<LoadInst>(Shuf->getOperand(OpIndex)); in widenSubvectorLoad()
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