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Searched refs:OpIdx (Results 1 – 25 of 157) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp69 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
75 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
81 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
87 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
106 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
112 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
118 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
228 getLdStUImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStUImm12OpValue() argument
249 getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAdrLabelOpValue() argument
275 getAddSubImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddSubImmOpValue() argument
312 getCondBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCondBranchTargetOpValue() argument
333 getLoadLiteralOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLoadLiteralOpValue() argument
353 getMemExtendOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemExtendOpValue() argument
362 getMoveWideImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMoveWideImmOpValue() argument
382 getTestBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTestBranchTargetOpValue() argument
403 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
431 getVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShifterOpValue() argument
456 getFixedPointScaleOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getFixedPointScaleOpValue() argument
464 getVecShiftR64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR64OpValue() argument
473 getVecShiftR32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR32OpValue() argument
482 getVecShiftR16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR16OpValue() argument
491 getVecShiftR8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR8OpValue() argument
500 getVecShiftL64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL64OpValue() argument
509 getVecShiftL32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL32OpValue() argument
518 getVecShiftL16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL16OpValue() argument
527 getVecShiftL8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL8OpValue() argument
537 EncodeRegAsMultipleOf(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeRegAsMultipleOf() argument
547 EncodePPR_p8to15(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodePPR_p8to15() argument
555 EncodeZPR2StridedRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeZPR2StridedRegisterClass() argument
565 EncodeZPR4StridedRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeZPR4StridedRegisterClass() argument
575 EncodeMatrixTileListRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeMatrixTileListRegisterClass() argument
584 encodeMatrixIndexGPR32(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeMatrixIndexGPR32() argument
592 getImm8OptLsl(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm8OptLsl() argument
610 getSVEIncDecImm(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSVEIncDecImm() argument
622 getMoveVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMoveVecShifterOpValue() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp95 uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
99 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
106 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
112 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
117 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
127 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
133 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
139 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
145 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
232 getLdStmModeOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStmModeOpValue() argument
592 EncodeAddrModeOpValues(const MCInst & MI,unsigned OpIdx,unsigned & Reg,unsigned & Imm,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeAddrModeOpValues() argument
621 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,unsigned FixupKind,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getBranchTargetOpValue() argument
659 getThumbBLTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBLTargetOpValue() argument
672 getThumbBLXTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBLXTargetOpValue() argument
684 getThumbBRTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBRTargetOpValue() argument
696 getThumbBCCTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBCCTargetOpValue() argument
708 getThumbCBTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbCBTargetOpValue() argument
737 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
751 getARMBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBranchTargetOpValue() argument
767 getARMBLTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBLTargetOpValue() argument
782 getARMBLXTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBLXTargetOpValue() argument
795 getThumbBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBranchTargetOpValue() argument
824 getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAdrLabelOpValue() argument
865 getT2AdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AdrLabelOpValue() argument
885 getITMaskOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getITMaskOpValue() argument
912 getThumbAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbAdrLabelOpValue() argument
925 getThumbAddrModeRegRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> &,const MCSubtargetInfo & STI) const getThumbAddrModeRegRegOpValue() argument
941 getMVEShiftImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMVEShiftImmOpValue() argument
975 getAddrModeImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeImm12OpValue() argument
1030 getT2ScaledImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2ScaledImmOpValue() argument
1061 getMveAddrModeRQOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMveAddrModeRQOpValue() argument
1081 getMveAddrModeQOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMveAddrModeQOpValue() argument
1112 getT2AddrModeImm8s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm8s4OpValue() argument
1154 getT2AddrModeImm7s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm7s4OpValue() argument
1181 getT2AddrModeImm0_1020s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm0_1020s4OpValue() argument
1193 getHiLoImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getHiLoImmOpValue() argument
1281 getLdStSORegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStSORegOpValue() argument
1315 getAddrMode2OffsetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode2OffsetOpValue() argument
1338 getPostIdxRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPostIdxRegOpValue() argument
1350 getAddrMode3OffsetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode3OffsetOpValue() argument
1370 getAddrMode3OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode3OpValue() argument
1407 getAddrModeThumbSPOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeThumbSPOpValue() argument
1423 getAddrModeISOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeISOpValue() argument
1438 getAddrModePCOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModePCOpValue() argument
1449 getAddrMode5OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode5OpValue() argument
1489 getAddrMode5FP16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode5FP16OpValue() argument
1528 getSORegRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSORegRegOpValue() argument
1576 getSORegImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSORegImmOpValue() argument
1685 getT2SORegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2SORegOpValue() argument
1926 getBFTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBFTargetOpValue() argument
1936 getBFAfterTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBFAfterTargetOpValue() argument
1958 getVPTMaskOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVPTMaskOpValue() argument
1990 getRestrictedCondCodeOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRestrictedCondCodeOpValue() argument
2018 getPowerTwoOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPowerTwoOpValue() argument
2028 getMVEPairVectorIndexOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMVEPairVectorIndexOpValue() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBankInfo.cpp115 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints() argument
121 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); in getRegBankFromConstraints()
126 Register Reg = MI.getOperand(OpIdx).getReg(); in getRegBankFromConstraints()
185 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in getInstrMappingImpl() local
186 ++OpIdx) { in getInstrMappingImpl()
187 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
206 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, MRI); in getInstrMappingImpl()
235 for (; OpIdx != EndIdx; ++OpIdx) { in getInstrMappingImpl()
236 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
253 OperandsMapping[OpIdx] = ValMapping; in getInstrMappingImpl()
[all …]
H A DBreakFalseDeps.cpp84 bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
89 bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref);
110 bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, in pickBestRegisterForUndef() argument
114 if (MI->isRegTiedToDefOperand(OpIdx)) in pickBestRegisterForUndef()
117 MachineOperand &MO = MI->getOperand(OpIdx); in pickBestRegisterForUndef()
138 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF); in pickBestRegisterForUndef()
175 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence() argument
177 MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg(); in shouldBreakDependence()
248 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
255 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) in processUndefReads()
[all …]
H A DMachineInstr.cpp737 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx) in isEquivalentDbgInstr() local
738 if (!getDebugOperand(OpIdx).isIdenticalTo(Other.getDebugOperand(OpIdx))) in isEquivalentDbgInstr()
874 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx() argument
877 assert(OpIdx < getNumOperands() && "OpIdx out of range"); in findInlineAsmFlagIdx()
880 if (OpIdx < InlineAsm::MIOp_FirstOperand) in findInlineAsmFlagIdx()
893 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx()
945 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() argument
954 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); in getRegClassConstraint()
956 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint()
961 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h156 uint64_t OpIdx = readULEB(); in executeMatchTable() local
162 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
193 << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx in executeMatchTable()
267 uint64_t OpIdx = readULEB(); in executeMatchTable() local
273 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
277 << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", " in executeMatchTable()
328 unsigned OpIdx = in executeMatchTable() local
333 << InsnID << "]->getOperand(" << OpIdx in executeMatchTable()
336 assert((State.MIs[InsnID]->getOperand(OpIdx).isImm() || in executeMatchTable()
337 State.MIs[InsnID]->getOperand(OpIdx).isCImm()) && in executeMatchTable()
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/
H A DGIMatchTree.h
H A DGIMatchTree.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMIRFormatter.cpp21 std::optional<unsigned int> OpIdx, int64_t Imm) const { in printImm() argument
25 assert(OpIdx == 0); in printImm()
29 MIRFormatter::printImm(OS, MI, OpIdx, Imm); in printImm()
37 const unsigned OpIdx, in parseImmMnemonic() argument
44 return parseSDelayAluImmMnemonic(OpIdx, Imm, Src, ErrorCallback); in parseImmMnemonic()
95 const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src, in parseSDelayAluImmMnemonic() argument
98 assert(OpIdx == 0); in parseSDelayAluImmMnemonic()
H A DAMDGPUInstructionSelector.h325 int OpIdx = -1) const;
328 int OpIdx) const;
331 int OpIdx) const;
334 int OpIdx) const;
337 int OpIdx) const;
340 int OpIdx) const;
342 int OpIdx) const;
344 int OpIdx) const;
346 int OpIdx) const;
349 int OpIdx) const;
[all …]
H A DAMDGPUMIRFormatter.h35 std::optional<unsigned> OpIdx,
40 virtual bool parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx,
57 const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src,
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/
H A DGlobalISelMatchTable.h830 unsigned OpIdx; variable
833 PredicateMatcher(PredicateKind Kind, unsigned InsnVarID, unsigned OpIdx = ~0)
834 : Kind(Kind), InsnVarID(InsnVarID), OpIdx(OpIdx) {} in Kind()
838 unsigned getOpIdx() const { return OpIdx; } in getOpIdx()
855 OpIdx == B.OpIdx; in isIdentical()
882 unsigned OpIdx) in OperandPredicateMatcher() argument
883 : PredicateMatcher(Kind, InsnVarID, OpIdx) {} in OperandPredicateMatcher()
907 SameOperandMatcher(unsigned InsnVarID, unsigned OpIdx, StringRef MatchingName, in SameOperandMatcher() argument
909 : OperandPredicateMatcher(OPM_SameOperand, InsnVarID, OpIdx), in SameOperandMatcher()
942 LLTOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const LLTCodeGen &Ty) in LLTOperandMatcher() argument
[all …]
H A DGlobalISelMatchTable.cpp1153 << MatchTable::Comment("OpIdx") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes()
1186 Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes()
1196 << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes()
1207 << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes()
1219 << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("TempTypeIdx") in emitPredicateOpcodes()
1230 << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes()
1256 Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes()
1268 << MatchTable::ULEB128Value(OpIdx) << MatchTable::LineBreak; in emitPredicateOpcodes()
1277 << MatchTable::ULEB128Value(OpIdx) << MatchTable::LineBreak; in emitPredicateOpcodes()
1288 << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp116 Register OpReg, unsigned OpIdx, in doInsertBitcast() argument
130 I.getOperand(OpIdx).setReg(NewReg); in doInsertBitcast()
152 MachineInstr &I, unsigned OpIdx, in validatePtrTypes() argument
156 Register OpReg = I.getOperand(OpIdx).getReg(); in validatePtrTypes()
179 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType); in validatePtrTypes()
188 constexpr unsigned OpIdx = 2; in validateGroupWaitEventsPtr() local
190 Register OpReg = I.getOperand(OpIdx).getReg(); in validateGroupWaitEventsPtr()
203 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType); in validateGroupWaitEventsPtr()
209 unsigned OpIdx) { in validateGroupAsyncCopyPtr() argument
211 Register OpReg = I.getOperand(OpIdx).getReg(); in validateGroupAsyncCopyPtr()
[all …]
H A DSPIRVEmitIntrinsics.cpp143 Type *deduceFunParamElementType(Function *F, unsigned OpIdx);
144 Type *deduceFunParamElementType(Function *F, unsigned OpIdx,
374 Function *CalledF, unsigned OpIdx) { in getPointeeTypeByCallInst() argument
377 OpIdx == 0) in getPointeeTypeByCallInst()
934 for (unsigned OpIdx = 0; OpIdx < Call.arg_size(); OpIdx++) in visitCallInst() local
935 Args.push_back(Call.getArgOperand(OpIdx)); in visitCallInst()
1159 for (unsigned OpIdx = 0; OpIdx < CalledF->arg_size(); ++OpIdx) { in insertPtrCastOrAssignTypeInstr() local
1160 Argument *CalledArg = CalledF->getArg(OpIdx); in insertPtrCastOrAssignTypeInstr()
1172 ElemTy = getPointeeTypeByCallInst(DemangledName, CalledF, OpIdx); in insertPtrCastOrAssignTypeInstr()
1192 for (unsigned OpIdx = 0; OpIdx < CI->arg_size(); OpIdx++) { in insertPtrCastOrAssignTypeInstr() local
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeEmitterGen.cpp122 unsigned OpIdx; in addCodeToMergeInOperand() local
125 OpIdx = CGI.Operands[SubOp.first].MIOperandNo + SubOp.second; in addCodeToMergeInOperand()
126 } else if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in addCodeToMergeInOperand()
128 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in addCodeToMergeInOperand()
135 if (CGI.Operands.isFlatOperandNotEmitted(OpIdx)) { in addCodeToMergeInOperand()
141 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in addCodeToMergeInOperand()
153 Case += " " + EncoderMethodName + "(MI, " + utostr(OpIdx); in addCodeToMergeInOperand()
156 Case += " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in addCodeToMergeInOperand()
162 " getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in addCodeToMergeInOperand()
166 utostr(OpIdx) + ")"; in addCodeToMergeInOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kMCCodeEmitter.cpp53 void encodeRelocImm(const MCInst &MI, unsigned OpIdx, unsigned InsertPos,
58 void encodePCRelImm(const MCInst &MI, unsigned OpIdx, unsigned InsertPos,
62 void encodeFPSYSSelect(const MCInst &MI, unsigned OpIdx, unsigned InsertPos,
117 void M68kMCCodeEmitter::encodeRelocImm(const MCInst &MI, unsigned OpIdx, in encodeRelocImm()
122 const MCOperand &MCO = MI.getOperand(OpIdx); in encodeRelocImm()
144 void M68kMCCodeEmitter::encodePCRelImm(const MCInst &MI, unsigned OpIdx, in encodePCRelImm()
148 const MCOperand &MCO = MI.getOperand(OpIdx); in encodePCRelImm()
179 void M68kMCCodeEmitter::encodeFPSYSSelect(const MCInst &MI, unsigned OpIdx, in getMachineOpValue()
183 MCRegister FPSysReg = MI.getOperand(OpIdx).getReg(); in getMachineOpValue()
113 encodeRelocImm(const MCInst & MI,unsigned OpIdx,unsigned InsertPos,APInt & Value,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeRelocImm() argument
140 encodePCRelImm(const MCInst & MI,unsigned OpIdx,unsigned InsertPos,APInt & Value,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodePCRelImm() argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp470 for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands(); in computeMapping() local
471 OpIdx != EndOpIdx; ++OpIdx) { in computeMapping()
472 const MachineOperand &MO = MI.getOperand(OpIdx); in computeMapping()
482 LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n'); in computeMapping()
484 InstrMapping.getOperandMapping(OpIdx); in computeMapping()
493 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, in computeMapping()
500 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); in computeMapping()
601 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
602 MachineOperand &MO = MI.getOperand(OpIdx); in applyMapping()
604 InstrMapping.getOperandMapping(OpIdx); in applyMapping()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SLSHardening.cpp460 for (unsigned OpIdx = BL->getNumExplicitOperands(); in convertBLRToBL() local
461 OpIdx < BL->getNumOperands(); OpIdx++) { in convertBLRToBL()
462 MachineOperand Op = BL->getOperand(OpIdx); in convertBLRToBL()
466 ImpLROpIdx = OpIdx; in convertBLRToBL()
468 ImpSPOpIdx = OpIdx; in convertBLRToBL()
481 for (unsigned OpIdx = 0; OpIdx < NumRegOperands; ++OpIdx) { in convertBLRToBL() local
482 MachineOperand &Op = BLR.getOperand(OpIdx); in convertBLRToBL()
H A DAArch64PromoteConstant.cpp273 unsigned OpIdx) { in shouldConvertUse() argument
276 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
280 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
284 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
287 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
291 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
295 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
299 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchOptWInstrs.cpp125 unsigned OpIdx = UserOp.getOperandNo(); in hasAllNBitUsers() local
222 if (OpIdx == 2) { in hasAllNBitUsers()
234 if (OpIdx == 2 && Bits >= Log2_32(ST.getGRLen())) in hasAllNBitUsers()
244 if (OpIdx == 0 && Bits >= 8) in hasAllNBitUsers()
253 if (OpIdx == 0 && Bits >= 16) in hasAllNBitUsers()
264 if (OpIdx == 0 && Bits >= 32) in hasAllNBitUsers()
270 if ((OpIdx == 1 && Bits >= 8) || (OpIdx == 2 && Bits >= 32)) in hasAllNBitUsers()
275 if ((OpIdx == 1 && Bits >= 16) || (OpIdx == 2 && Bits >= 32)) in hasAllNBitUsers()
280 if (OpIdx == 2 && Bits >= 32) in hasAllNBitUsers()
304 if (OpIdx != 1) in hasAllNBitUsers()
/freebsd/contrib/llvm-project/llvm/include/llvm/SandboxIR/
H A DSandboxIR.h330 Use getOperandUseDefault(unsigned OpIdx, bool Verify) const;
334 virtual Use getOperandUseInternal(unsigned OpIdx, bool Verify) const = 0;
378 Value *getOperand(unsigned OpIdx) const { return getOperandUse(OpIdx).get(); } in getOperand() argument
381 Use getOperandUse(unsigned OpIdx) const { in getOperandUse() argument
382 return getOperandUseInternal(OpIdx, /*Verify=*/true); in getOperandUse()
411 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal() argument
412 return getOperandUseDefault(OpIdx, Verify); in getOperandUseInternal()
580 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal() argument
581 return getOperandUseDefault(OpIdx, Verify); in getOperandUseInternal()
625 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCInstPrinter.cpp64 const MCRegisterInfo &MRI, unsigned &OpIdx, in matchAliasCondition() argument
91 const MCOperand &Opnd = MI.getOperand(OpIdx); in matchAliasCondition()
92 ++OpIdx; in matchAliasCondition()
148 unsigned OpIdx = 0; in matchAliasPatterns() local
151 return matchAliasCondition(*MI, STI, MRI, OpIdx, M, C, in matchAliasPatterns()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenInstruction.cpp200 unsigned OpIdx; in getOperandNamed() local
201 if (hasOperandNamed(Name, OpIdx)) in getOperandNamed()
202 return OpIdx; in getOperandNamed()
211 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { in hasOperandNamed()
215 OpIdx = i; in hasOperandNamed()
252 unsigned OpIdx; in ParseOperandName() local
266 OpIdx = getOperandNamed(OpName); in ParseOperandName()
270 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && in ParseOperandName()
279 return std::pair(OpIdx, 0U); in ParseOperandName()
283 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; in ParseOperandName()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp122 for (unsigned OpIdx = 0; OpIdx < MID.getNumOperands(); OpIdx++) { in has4RegOps() local
123 const TargetRegisterClass *RC = TII->getRegClass(MID, OpIdx, TRI, MF); in has4RegOps()
126 if (OpIdx >= MID.getNumDefs() && in has4RegOps()
127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()

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