| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 66 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, 72 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 78 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, 84 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 90 uint32_t getCondCompBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 96 uint32_t getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx, 102 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, 109 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, 115 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 121 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 93 uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx, 97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 112 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints() argument 118 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); in getRegBankFromConstraints() 123 Register Reg = MI.getOperand(OpIdx).getReg(); in getRegBankFromConstraints() 182 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in getInstrMappingImpl() local 183 ++OpIdx) { in getInstrMappingImpl() 184 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl() 203 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, MRI); in getInstrMappingImpl() 233 for (; OpIdx != EndIdx; ++OpIdx) { in getInstrMappingImpl() 234 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl() 251 OperandsMapping[OpIdx] = ValMapping; in getInstrMappingImpl() [all …]
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| H A D | BreakFalseDeps.cpp | 83 bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, 88 bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref); 109 bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, in pickBestRegisterForUndef() argument 113 if (MI->isRegTiedToDefOperand(OpIdx)) in pickBestRegisterForUndef() 116 MachineOperand &MO = MI->getOperand(OpIdx); in pickBestRegisterForUndef() 137 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF); in pickBestRegisterForUndef() 174 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence() argument 176 MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg(); in shouldBreakDependence() 247 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local 254 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) in processUndefReads() [all …]
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| H A D | MachineInstr.cpp | 744 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx) in isEquivalentDbgInstr() local 745 if (!getDebugOperand(OpIdx).isIdenticalTo(Other.getDebugOperand(OpIdx))) in isEquivalentDbgInstr() 901 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx() argument 904 assert(OpIdx < getNumOperands() && "OpIdx out of range"); in findInlineAsmFlagIdx() 907 if (OpIdx < InlineAsm::MIOp_FirstOperand) in findInlineAsmFlagIdx() 920 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx() 972 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() argument 981 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); in getRegClassConstraint() 983 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint() 988 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint() [all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GIMatchTableExecutorImpl.h | 156 uint64_t OpIdx = readULEB(); in executeMatchTable() local 162 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable() 193 << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx in executeMatchTable() 268 uint64_t OpIdx = readULEB(); in executeMatchTable() local 274 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable() 278 << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", " in executeMatchTable() 346 unsigned OpIdx = in executeMatchTable() local 351 << InsnID << "]->getOperand(" << OpIdx in executeMatchTable() 354 assert((State.MIs[InsnID]->getOperand(OpIdx).isImm() || in executeMatchTable() 355 State.MIs[InsnID]->getOperand(OpIdx).isCImm()) && in executeMatchTable() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.h | 333 int OpIdx = -1) const; 336 int OpIdx) const; 338 int OpIdx) const; 341 int OpIdx) const; 345 int OpIdx) const; 349 int OpIdx) const; 353 int OpIdx) const; 357 int OpIdx) const; 360 const MachineInstr &MI, int OpIdx) const; 363 const MachineInstr &MI, int OpIdx) const; [all …]
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| H A D | AMDGPUMIRFormatter.cpp | 20 std::optional<unsigned int> OpIdx, int64_t Imm) const { in printImm() argument 24 assert(OpIdx == 0); in printImm() 28 MIRFormatter::printImm(OS, MI, OpIdx, Imm); in printImm() 36 const unsigned OpIdx, in parseImmMnemonic() argument 43 return parseSDelayAluImmMnemonic(OpIdx, Imm, Src, ErrorCallback); in parseImmMnemonic() 94 const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src, in parseSDelayAluImmMnemonic() argument 97 assert(OpIdx == 0); in parseSDelayAluImmMnemonic()
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| H A D | AMDGPUMIRFormatter.h | 35 std::optional<unsigned> OpIdx, 40 virtual bool parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, 57 const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src,
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/ |
| H A D | GIMatchTree.h | |
| H A D | GIMatchTree.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kMCCodeEmitter.cpp | 53 void encodeRelocImm(const MCInst &MI, unsigned OpIdx, unsigned InsertPos, 58 void encodePCRelImm(const MCInst &MI, unsigned OpIdx, unsigned InsertPos, 62 void encodeFPSYSSelect(const MCInst &MI, unsigned OpIdx, unsigned InsertPos, 66 void encodeInverseMoveMask(const MCInst &MI, unsigned OpIdx, 127 void M68kMCCodeEmitter::encodeRelocImm(const MCInst &MI, unsigned OpIdx, in encodeRelocImm() argument 132 const MCOperand &MCO = MI.getOperand(OpIdx); in encodeRelocImm() 152 void M68kMCCodeEmitter::encodePCRelImm(const MCInst &MI, unsigned OpIdx, in encodePCRelImm() argument 156 const MCOperand &MCO = MI.getOperand(OpIdx); in encodePCRelImm() 186 void M68kMCCodeEmitter::encodeFPSYSSelect(const MCInst &MI, unsigned OpIdx, in encodeFPSYSSelect() argument 190 MCRegister FPSysReg = MI.getOperand(OpIdx).getReg(); in encodeFPSYSSelect() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeInfo.cpp | 34 unsigned OpIdx, EVT ExpectedVT) { in checkOperandType() argument 35 EVT ActualVT = N->getOperand(OpIdx).getValueType(); in checkOperandType() 39 "operand #" + Twine(OpIdx) + " has invalid type; expected " + in checkOperandType() 120 for (unsigned OpIdx = VarOpStart; OpIdx != VarOpEnd; ++OpIdx) { in verifyNode() local 121 unsigned OpOpcode = N->getOperand(OpIdx).getOpcode(); in verifyNode() 124 "variadic operand #" + Twine(OpIdx) + in verifyNode()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/ |
| H A D | GlobalISelMatchTable.h | 844 unsigned OpIdx; variable 847 PredicateMatcher(PredicateKind Kind, unsigned InsnVarID, unsigned OpIdx = ~0) 848 : Kind(Kind), InsnVarID(InsnVarID), OpIdx(OpIdx) {} in Kind() 852 unsigned getOpIdx() const { return OpIdx; } in getOpIdx() 869 OpIdx == B.OpIdx; in isIdentical() 896 unsigned OpIdx) in OperandPredicateMatcher() argument 897 : PredicateMatcher(Kind, InsnVarID, OpIdx) {} in OperandPredicateMatcher() 921 SameOperandMatcher(unsigned InsnVarID, unsigned OpIdx, StringRef MatchingName, in SameOperandMatcher() argument 923 : OperandPredicateMatcher(OPM_SameOperand, InsnVarID, OpIdx), in SameOperandMatcher() 956 LLTOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const LLTCodeGen &Ty) in LLTOperandMatcher() argument [all …]
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| H A D | GlobalISelMatchTable.cpp | 1146 << MatchTable::Comment("OpIdx") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes() 1179 Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes() 1190 << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes() 1201 << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes() 1213 << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("TempTypeIdx") in emitPredicateOpcodes() 1224 << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes() 1250 Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes() 1262 << MatchTable::ULEB128Value(OpIdx) << MatchTable::LineBreak; in emitPredicateOpcodes() 1271 << MatchTable::ULEB128Value(OpIdx) << MatchTable::LineBreak; in emitPredicateOpcodes() 1282 << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) in emitPredicateOpcodes() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/SandboxIR/ |
| H A D | User.cpp | 58 Use User::getOperandUseDefault(unsigned OpIdx, bool Verify) const { in getOperandUseDefault() argument 59 assert((!Verify || OpIdx < getNumOperands()) && "Out of bounds!"); in getOperandUseDefault() 62 if (OpIdx != getNumOperands()) in getOperandUseDefault() 63 LLVMUse = &cast<llvm::User>(Val)->getOperandUse(OpIdx); in getOperandUseDefault() 102 for (auto OpIdx : seq<unsigned>(0, getNumOperands())) { in replaceUsesOfWith() local 103 auto Use = getOperandUse(OpIdx); in replaceUsesOfWith()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/SandboxIR/ |
| H A D | User.h | 67 Use getOperandUseDefault(unsigned OpIdx, bool Verify) const; 71 virtual Use getOperandUseInternal(unsigned OpIdx, bool Verify) const = 0; 123 Value *getOperand(unsigned OpIdx) const { return getOperandUse(OpIdx).get(); } in getOperand() argument 126 Use getOperandUse(unsigned OpIdx) const { in getOperandUse() argument 127 return getOperandUseInternal(OpIdx, /*Verify=*/true); in getOperandUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyInstPrinter.cpp | 155 unsigned OpIdx = 1; in printInst() local 156 const MCOperand &Op = MI->getOperand(OpIdx++); in printInst() 159 int64_t CatchOpcode = MI->getOperand(OpIdx++).getImm(); in printInst() 162 OpIdx++; // Skip tag in printInst() 163 PrintBranchAnnotation(MI->getOperand(OpIdx++), Printed); in printInst() 395 unsigned OpIdx = OpNo; in printCatchList() local 396 const MCOperand &Op = MI->getOperand(OpIdx++); in printCatchList() 414 const MCOperand &Op = MI->getOperand(OpIdx++); in printCatchList() 419 PrintTagOp(MI->getOperand(OpIdx++)); in printCatchList() 423 PrintTagOp(MI->getOperand(OpIdx++)); in printCatchList() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVISelLowering.cpp | 147 Register OpReg, unsigned OpIdx, in doInsertBitcast() argument 159 I.getOperand(OpIdx).setReg(NewReg); in doInsertBitcast() 180 MachineInstr &I, unsigned OpIdx, in validatePtrTypes() argument 184 Register OpReg = I.getOperand(OpIdx).getReg(); in validatePtrTypes() 207 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType); in validatePtrTypes() 216 constexpr unsigned OpIdx = 2; in validateGroupWaitEventsPtr() local 218 Register OpReg = I.getOperand(OpIdx).getReg(); in validateGroupWaitEventsPtr() 231 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType); in validateGroupWaitEventsPtr() 260 MachineInstr &I, unsigned OpIdx) { in validatePtrUnwrapStructField() argument 262 Register OpReg = I.getOperand(OpIdx).getReg(); in validatePtrUnwrapStructField() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 470 for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands(); in computeMapping() local 471 OpIdx != EndOpIdx; ++OpIdx) { in computeMapping() 472 const MachineOperand &MO = MI.getOperand(OpIdx); in computeMapping() 482 LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n'); in computeMapping() 484 InstrMapping.getOperandMapping(OpIdx); in computeMapping() 493 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, in computeMapping() 500 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); in computeMapping() 601 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local 602 MachineOperand &MO = MI.getOperand(OpIdx); in applyMapping() 604 InstrMapping.getOperandMapping(OpIdx); in applyMapping() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 135 int OpIdx) const; 137 int OpIdx) const; 139 int OpIdx) const; 141 int OpIdx) const; 143 int OpIdx) const; 146 int OpIdx) const; 148 const MachineInstr &MI, int OpIdx) const; 151 int OpIdx) const; 153 int OpIdx) const; 221 unsigned OpIdx = UserOp.getOperandNo(); in hasAllNBitUsers() local [all …]
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeEmitterGen.cpp | 125 unsigned OpIdx; in addCodeToMergeInOperand() local 127 OpIdx = CGI.Operands[SubOp->first].MIOperandNo + SubOp->second; in addCodeToMergeInOperand() 130 OpIdx = CGI.Operands[*MayBeOpIdx].MIOperandNo; in addCodeToMergeInOperand() 137 if (CGI.Operands.isFlatOperandNotEmitted(OpIdx)) { in addCodeToMergeInOperand() 143 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in addCodeToMergeInOperand() 157 CaseOS << EncoderMethodName << "(MI, " + utostr(OpIdx) << ", op"; in addCodeToMergeInOperand() 159 CaseOS << "op = " << EncoderMethodName << "(MI, " << utostr(OpIdx); in addCodeToMergeInOperand() 165 " getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in addCodeToMergeInOperand() 169 utostr(OpIdx) + ")"; in addCodeToMergeInOperand() 275 BitOffsetCase += " case " + utostr(OpIdx) + ":\n"; in addCodeToMergeInOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SLSHardening.cpp | 460 for (unsigned OpIdx = BL->getNumExplicitOperands(); in convertBLRToBL() local 461 OpIdx < BL->getNumOperands(); OpIdx++) { in convertBLRToBL() 462 MachineOperand Op = BL->getOperand(OpIdx); in convertBLRToBL() 466 ImpLROpIdx = OpIdx; in convertBLRToBL() 468 ImpSPOpIdx = OpIdx; in convertBLRToBL() 481 for (unsigned OpIdx = 0; OpIdx < NumRegOperands; ++OpIdx) { in convertBLRToBL() local 482 MachineOperand &Op = BLR.getOperand(OpIdx); in convertBLRToBL()
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| H A D | AArch64PromoteConstant.cpp | 269 unsigned OpIdx) { in shouldConvertUse() argument 272 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse() 276 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse() 280 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse() 283 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse() 287 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse() 291 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse() 295 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchOptWInstrs.cpp | 125 unsigned OpIdx = UserOp.getOperandNo(); in hasAllNBitUsers() local 252 if (OpIdx == 2) { in hasAllNBitUsers() 264 if (OpIdx == 2 && Bits >= Log2_32(ST.getGRLen())) in hasAllNBitUsers() 274 if (OpIdx == 0 && Bits >= 8) in hasAllNBitUsers() 283 if (OpIdx == 0 && Bits >= 16) in hasAllNBitUsers() 294 if (OpIdx == 0 && Bits >= 32) in hasAllNBitUsers() 300 if ((OpIdx == 1 && Bits >= 8) || (OpIdx == 2 && Bits >= 32)) in hasAllNBitUsers() 305 if ((OpIdx == 1 && Bits >= 16) || (OpIdx == 2 && Bits >= 32)) in hasAllNBitUsers() 310 if (OpIdx == 2 && Bits >= 32) in hasAllNBitUsers() 334 if (OpIdx != 1) in hasAllNBitUsers()
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