Searched refs:OpEntry (Results 1 – 3 of 3) sorted by relevance
1950 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem() local1960 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()1962 if (OpEntry.OpSignExtend) { in X86SelectDivRem()1963 if (OpEntry.IsOpSigned) in X86SelectDivRem()1965 TII.get(OpEntry.OpSignExtend)); in X86SelectDivRem()1991 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()2003 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()2021 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()
1783 const MulDivRemEntry::MulDivRemResult &OpEntry = in selectMulDivRem() local1796 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), in selectMulDivRem()1801 if (OpEntry.OpSignExtend) { in selectMulDivRem()1802 if (OpEntry.IsOpSigned) in selectMulDivRem()1804 TII.get(OpEntry.OpSignExtend)); in selectMulDivRem()1832 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpMulDivRem)) in selectMulDivRem()1843 if (OpEntry.ResultReg == X86::AH && STI.is64Bit()) { in selectMulDivRem()1862 .addReg(OpEntry.ResultReg); in selectMulDivRem()