Searched refs:OpEntry (Results 1 – 3 of 3) sorted by relevance
1944 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem() local1954 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()1956 if (OpEntry.OpSignExtend) { in X86SelectDivRem()1957 if (OpEntry.IsOpSigned) in X86SelectDivRem()1959 TII.get(OpEntry.OpSignExtend)); in X86SelectDivRem()1985 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()1997 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()2015 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()
1743 const MulDivRemEntry::MulDivRemResult &OpEntry = in selectMulDivRem() local1756 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), in selectMulDivRem()1761 if (OpEntry.OpSignExtend) { in selectMulDivRem()1762 if (OpEntry.IsOpSigned) in selectMulDivRem()1764 TII.get(OpEntry.OpSignExtend)); in selectMulDivRem()1792 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpMulDivRem)) in selectMulDivRem()1803 if (OpEntry.ResultReg == X86::AH && STI.is64Bit()) { in selectMulDivRem()1822 .addReg(OpEntry.ResultReg); in selectMulDivRem()