Home
last modified time | relevance | path

Searched refs:OpDesc (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h646 ComponentProps(const MCInstrDesc &OpDesc);
789 ComponentInfo(const MCInstrDesc &OpDesc,
791 : ComponentLayout(Kind), ComponentProps(OpDesc) {} in ComponentLayout()
794 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps) in ComponentInfo() argument
795 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {} in ComponentInfo()
1511 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1514 bool isDPALU_DPP(const MCInstrDesc &OpDesc);
H A DAMDGPUBaseInfo.cpp666 ComponentProps::ComponentProps(const MCInstrDesc &OpDesc) { in ComponentProps() argument
667 assert(OpDesc.getNumDefs() == Component::DST_NUM); in ComponentProps()
669 assert(OpDesc.getOperandConstraint(Component::SRC0, MCOI::TIED_TO) == -1); in ComponentProps()
670 assert(OpDesc.getOperandConstraint(Component::SRC1, MCOI::TIED_TO) == -1); in ComponentProps()
671 auto TiedIdx = OpDesc.getOperandConstraint(Component::SRC2, MCOI::TIED_TO); in ComponentProps()
675 SrcOperandsNum = OpDesc.getNumOperands() - OpDesc.getNumDefs(); in ComponentProps()
678 auto OperandsNum = OpDesc.getNumOperands(); in ComponentProps()
681 if (OpDesc.operands()[CompOprIdx].OperandType == AMDGPU::OPERAND_KIMM32) { in ComponentProps()
2956 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc) { in hasAny64BitVGPROperands() argument
2959 int Idx = getNamedOperandIdx(OpDesc.getOpcode(), OpName); in hasAny64BitVGPROperands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/FuzzMutate/
H A DIRMutator.cpp143 auto OpDesc = chooseOperation(Srcs[0], IB); in mutate() local
145 if (!OpDesc) in mutate()
148 for (const auto &Pred : ArrayRef(OpDesc->SourcePreds).slice(1)) in mutate()
151 if (Value *Op = OpDesc->BuilderFunc(Srcs, Insts[IP])) { in mutate()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1742 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); in storeRegToStackSlot() local
1750 BuildMI(MBB, MI, DL, OpDesc) in storeRegToStackSlot()
1969 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize)); in loadRegFromStackSlot() local
1977 BuildMI(MBB, MI, DL, OpDesc, DestReg) in loadRegFromStackSlot()
2348 const MCInstrDesc &OpDesc = get(Opc); in expandPostRAPseudo() local
2355 BuildMI(MBB, MI, DL, OpDesc) in expandPostRAPseudo()
2362 OpDesc.getNumOperands() + OpDesc.implicit_uses().size(); in expandPostRAPseudo()
2391 const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect_write); in expandPostRAPseudo() local
2393 BuildMI(MBB, MI, DL, OpDesc) in expandPostRAPseudo()
2401 OpDesc.getNumOperands() + OpDesc.implicit_uses().size(); in expandPostRAPseudo()