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Searched refs:OpDesc (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp798 ComponentProps::ComponentProps(const MCInstrDesc &OpDesc, bool VOP3Layout) { in ComponentProps() argument
799 assert(OpDesc.getNumDefs() == Component::DST_NUM); in ComponentProps()
801 assert(OpDesc.getOperandConstraint(Component::SRC0, MCOI::TIED_TO) == -1); in ComponentProps()
802 assert(OpDesc.getOperandConstraint(Component::SRC1, MCOI::TIED_TO) == -1); in ComponentProps()
803 auto TiedIdx = OpDesc.getOperandConstraint(Component::SRC2, MCOI::TIED_TO); in ComponentProps()
806 Opcode = OpDesc.getOpcode(); in ComponentProps()
808 IsVOP3 = VOP3Layout || (OpDesc.TSFlags & SIInstrFlags::VOP3); in ComponentProps()
822 } else if (isSISrcFPOperand(OpDesc, in ComponentProps()
831 if (OpDesc.TSFlags & SIInstrFlags::VOP3) in ComponentProps()
834 auto OperandsNum = OpDesc.getNumOperands(); in ComponentProps()
[all …]
H A DAMDGPUBaseInfo.h689 ComponentProps(const MCInstrDesc &OpDesc, bool VOP3Layout = false);
870 ComponentInfo(const MCInstrDesc &OpDesc,
873 : ComponentProps(OpDesc, VOP3Layout), in ComponentProps() argument
877 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps,
879 : ComponentProps(OpDesc, VOP3Layout), in ComponentProps() argument
1731 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1734 bool isDPALU_DPP(const MCInstrDesc &OpDesc);
/freebsd/contrib/llvm-project/llvm/lib/FuzzMutate/
H A DIRMutator.cpp176 auto OpDesc = chooseOperation(Srcs[0], IB); in mutate() local
178 if (!OpDesc) in mutate()
181 for (const auto &Pred : ArrayRef(OpDesc->SourcePreds).slice(1)) in mutate()
184 if (Value *Op = OpDesc->BuilderFunc(Srcs, Insts[IP]->getIterator())) { in mutate()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp525 for (auto [OpNo, OpDesc] : enumerate(Desc.operands())) { in decodeImmOperands()
531 bool IsSrc = AMDGPU::OPERAND_SRC_FIRST <= OpDesc.OperandType && in decodeImmOperands()
532 OpDesc.OperandType <= AMDGPU::OPERAND_SRC_LAST; in decodeImmOperands()
533 if (!IsSrc && OpDesc.OperandType != MCOI::OPERAND_REGISTER) in decodeImmOperands()
547 Op = decodeLiteralConstant(OpDesc.OperandType == in decodeImmOperands()
554 switch (OpDesc.OperandType) { in decodeImmOperands()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1754 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); in storeRegToStackSlot() local
1762 BuildMI(MBB, MI, DL, OpDesc) in storeRegToStackSlot()
1984 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize)); in loadRegFromStackSlot() local
1992 BuildMI(MBB, MI, DL, OpDesc, DestReg) in loadRegFromStackSlot()
2354 const MCInstrDesc &OpDesc = get(Opc); in expandPostRAPseudo() local
2361 BuildMI(MBB, MI, DL, OpDesc) in expandPostRAPseudo()
2368 OpDesc.getNumOperands() + OpDesc.implicit_uses().size(); in expandPostRAPseudo()
2397 const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect_write); in expandPostRAPseudo() local
2399 BuildMI(MBB, MI, DL, OpDesc) in expandPostRAPseudo()
2407 OpDesc.getNumOperands() + OpDesc.implicit_uses().size(); in expandPostRAPseudo()