| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 623 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
628 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
632 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
657 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
662 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
667 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
678 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
683 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
686 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
697 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 6308 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
6310 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
6312 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
6329 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
6341 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
6351 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
6372 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
6374 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
6376 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
6393 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 2588 const T4 &Op4) {
2590 m_Argument<4>(Op4));
2597 const T4 &Op4, const T5 &Op5) {
2598 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3, Op4),
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1713 SDValue Op4 = Node->getOperand(4); in Select() local
1715 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1614 SDValue Op3, SDValue Op4);
1616 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 506 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
507 (inst $Op1, $Op2, $Op3, $Op4)>;
535 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
536 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
2566 …def : Pat<(nxv8f16 (op nxv8i1:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, nxv8f16:$Op4, (i32 complexrotateop…
2567 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
2568 …def : Pat<(nxv4f32 (op nxv4i1:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, nxv4f32:$Op4, (i32 complexrotateop…
2569 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
2570 …def : Pat<(nxv2f64 (op nxv2i1:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, nxv2f64:$Op4, (i32 complexrotateop…
2571 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 6591 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
6600 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
6609 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6767 auto &Op4 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]); in tryConvertingToTwoOperandForm() local
6768 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6772 auto Op4Reg = Op4.getReg(); in tryConvertingToTwoOperandForm()
6816 LastOp = &Op4; in tryConvertingToTwoOperandForm()
6837 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 10542 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
10543 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
10549 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
10550 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|