Searched refs:Op32 (Results 1 – 4 of 4) sorted by relevance
7192 static bool PeepholePPC64ZExtGather(SDValue Op32, in PeepholePPC64ZExtGather() argument7194 if (!Op32.isMachineOpcode()) in PeepholePPC64ZExtGather()7203 if ((Op32.getMachineOpcode() == PPC::RLWINM || in PeepholePPC64ZExtGather()7204 Op32.getMachineOpcode() == PPC::RLWNM) && in PeepholePPC64ZExtGather()7205 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) { in PeepholePPC64ZExtGather()7206 ToPromote.insert(Op32.getNode()); in PeepholePPC64ZExtGather()7211 if (Op32.getMachineOpcode() == PPC::SLW || in PeepholePPC64ZExtGather()7212 Op32.getMachineOpcode() == PPC::SRW) { in PeepholePPC64ZExtGather()7213 ToPromote.insert(Op32.getNode()); in PeepholePPC64ZExtGather()7219 if (Op32.getMachineOpcode() == PPC::LI || in PeepholePPC64ZExtGather()[all …]
998 int Op32 = AMDGPU::getVOPe32(MI.getOpcode()); in run() local1000 if (TII->isVOPC(Op32)) { in run()1024 if (Op32 == AMDGPU::V_CNDMASK_B32_e32) { in run()1085 MachineInstr *Inst32 = TII->buildShrunkInst(MI, Op32); in run()
639 int Op32 = Fold.ShrinkOpcode; in updateOperand() local649 MachineInstr *Inst32 = TII->buildShrunkInst(*MI, Op32); in updateOperand()849 int Op32 = -1; in tryAddToFoldList() local869 Op32 = AMDGPU::getVOPe32(MaybeCommutedOpc); in tryAddToFoldList()873 Op32); in tryAddToFoldList()
4534 int Op32 = AMDGPU::getVOPe32(Opcode); in hasVALU32BitEncoding() local4535 if (Op32 == -1) in hasVALU32BitEncoding()4538 return pseudoToMCOpcode(Op32) != -1; in hasVALU32BitEncoding()4636 unsigned Op32) const { in buildShrunkInst()4639 const MCInstrDesc &Op32Desc = get(Op32); in buildShrunkInst()4661 if (AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2) == -1) { in buildShrunkInst()