Searched refs:Op32 (Results 1 – 4 of 4) sorted by relevance
7179 static bool PeepholePPC64ZExtGather(SDValue Op32, in PeepholePPC64ZExtGather() argument7181 if (!Op32.isMachineOpcode()) in PeepholePPC64ZExtGather()7190 if ((Op32.getMachineOpcode() == PPC::RLWINM || in PeepholePPC64ZExtGather()7191 Op32.getMachineOpcode() == PPC::RLWNM) && in PeepholePPC64ZExtGather()7192 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) { in PeepholePPC64ZExtGather()7193 ToPromote.insert(Op32.getNode()); in PeepholePPC64ZExtGather()7198 if (Op32.getMachineOpcode() == PPC::SLW || in PeepholePPC64ZExtGather()7199 Op32.getMachineOpcode() == PPC::SRW) { in PeepholePPC64ZExtGather()7200 ToPromote.insert(Op32.getNode()); in PeepholePPC64ZExtGather()7206 if (Op32.getMachineOpcode() == PPC::LI || in PeepholePPC64ZExtGather()[all …]
948 int Op32 = AMDGPU::getVOPe32(MI.getOpcode()); in runOnMachineFunction() local950 if (TII->isVOPC(Op32)) { in runOnMachineFunction()974 if (Op32 == AMDGPU::V_CNDMASK_B32_e32) { in runOnMachineFunction()1033 MachineInstr *Inst32 = TII->buildShrunkInst(MI, Op32); in runOnMachineFunction()
384 int Op32 = Fold.ShrinkOpcode; in updateOperand() local394 MachineInstr *Inst32 = TII->buildShrunkInst(*MI, Op32); in updateOperand()577 int Op32 = -1; in tryAddToFoldList() local597 Op32 = AMDGPU::getVOPe32(MaybeCommutedOpc); in tryAddToFoldList()600 appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, true, Op32); in tryAddToFoldList()
4390 int Op32 = AMDGPU::getVOPe32(Opcode); in hasVALU32BitEncoding() local4391 if (Op32 == -1) in hasVALU32BitEncoding()4394 return pseudoToMCOpcode(Op32) != -1; in hasVALU32BitEncoding()4487 unsigned Op32) const { in buildShrunkInst()4490 const MCInstrDesc &Op32Desc = get(Op32); in buildShrunkInst()4512 if (AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2) == -1) { in buildShrunkInst()