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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp18377 Register Op2Reg4 = Second.getOperand(4).getReg(); in EmitLoweredCascadedSelect()
18379 .addReg(Op2Reg4) in EmitLoweredCascadedSelect()
18374 Register Op2Reg4 = Second.getOperand(4).getReg(); EmitLoweredCascadedSelect() local