Searched refs:Op2Reg (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CmovConversion.cpp | 838 Register Op2Reg = MIIt->getOperand(2).getReg(); in convertCmovInstsToBranches() local
844 std::swap(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
850 auto Op2Itr = RegRewriteTable.find(Op2Reg); in convertCmovInstsToBranches()
852 Op2Reg = Op2Itr->second.second; in convertCmovInstsToBranches()
860 .addReg(Op2Reg) in convertCmovInstsToBranches()
872 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
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| H A D | X86InstructionSelector.cpp | |
| H A D | X86InstrInfo.cpp | 2786 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg(); in findThreeSrcCommutedOpIndices() local
2798 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg()) in findThreeSrcCommutedOpIndices()
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| H A D | X86ISelLowering.cpp | 34906 Register Op2Reg = MIIt->getOperand(2).getReg(); in createPHIsForCMOVsInSinkBB() local
34912 std::swap(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
34917 if (RegRewriteTable.contains(Op2Reg)) in createPHIsForCMOVsInSinkBB()
34918 Op2Reg = RegRewriteTable[Op2Reg].second; in createPHIsForCMOVsInSinkBB()
34924 .addReg(Op2Reg) in createPHIsForCMOVsInSinkBB()
34928 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
35069 Register Op2Reg = FirstCMOV.getOperand(2).getReg(); in EmitLoweredCascadedSelect() local
35074 .addReg(Op2Reg) in EmitLoweredCascadedSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1630 unsigned Op2Reg = 0; in SelectSelect() local
1632 Op2Reg = getRegForValue(I->getOperand(2)); in SelectSelect()
1633 if (Op2Reg == 0) return false; in SelectSelect()
1657 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1); in SelectSelect()
1661 .addReg(Op2Reg) in SelectSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1619 const Register Op2Reg = I.getOperand(2).getReg(); in selectMulDivRem() local
1622 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectMulDivRem()
1748 !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || in selectMulDivRem()
1793 .addReg(Op2Reg); in selectMulDivRem()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 3273 Register Op2Reg = MIIt->getOperand(2).getReg(); in EmitLoweredSelect() local
3279 std::swap(Op1Reg, Op2Reg); in EmitLoweredSelect()
3284 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end()) in EmitLoweredSelect()
3285 Op2Reg = RegRewriteTable[Op2Reg].second; in EmitLoweredSelect()
3291 .addReg(Op2Reg) in EmitLoweredSelect()
3295 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in EmitLoweredSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 8470 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] = in lowerSelect()
8478 Op2Reg = MIRBuilder.buildPtrToInt(NewTy, Op2Reg).getReg(0); in lowerSelect()
8515 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); in lowerSelect()
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