Searched refs:Op2Reg (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CmovConversion.cpp | 835 Register Op2Reg = MIIt->getOperand(2).getReg(); in convertCmovInstsToBranches() local
841 std::swap(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
847 auto Op2Itr = RegRewriteTable.find(Op2Reg); in convertCmovInstsToBranches()
849 Op2Reg = Op2Itr->second.second; in convertCmovInstsToBranches()
857 .addReg(Op2Reg) in convertCmovInstsToBranches()
869 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
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| H A D | X86InstructionSelector.cpp | |
| H A D | X86InstrInfo.cpp | 2771 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg(); in findThreeSrcCommutedOpIndices() local
2783 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg()) in findThreeSrcCommutedOpIndices()
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| H A D | X86ISelLowering.cpp | 36160 Register Op2Reg = MIIt->getOperand(2).getReg(); in createPHIsForCMOVsInSinkBB() local
36166 std::swap(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
36171 if (auto It = RegRewriteTable.find(Op2Reg); It != RegRewriteTable.end()) in createPHIsForCMOVsInSinkBB()
36172 Op2Reg = It->second.second; in createPHIsForCMOVsInSinkBB()
36178 .addReg(Op2Reg) in createPHIsForCMOVsInSinkBB()
36182 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
36323 Register Op2Reg = FirstCMOV.getOperand(2).getReg(); in EmitLoweredCascadedSelect() local
36328 .addReg(Op2Reg) in EmitLoweredCascadedSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1687 Register Op2Reg; in SelectSelect() local
1689 Op2Reg = getRegForValue(I->getOperand(2)); in SelectSelect()
1690 if (!Op2Reg) in SelectSelect()
1715 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1); in SelectSelect()
1719 .addReg(Op2Reg) in SelectSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1659 const Register Op2Reg = I.getOperand(2).getReg(); in selectMulDivRem() local
1662 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectMulDivRem()
1788 !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || in selectMulDivRem()
1833 .addReg(Op2Reg); in selectMulDivRem()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 3273 Register Op2Reg = MIIt->getOperand(2).getReg(); in EmitLoweredSelect() local
3279 std::swap(Op1Reg, Op2Reg); in EmitLoweredSelect()
3284 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end()) in EmitLoweredSelect()
3285 Op2Reg = RegRewriteTable[Op2Reg].second; in EmitLoweredSelect()
3291 .addReg(Op2Reg) in EmitLoweredSelect()
3295 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in EmitLoweredSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 9416 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] = in lowerSelect()
9424 Op2Reg = MIRBuilder.buildPtrToInt(NewTy, Op2Reg).getReg(0); in lowerSelect()
9461 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); in lowerSelect()
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