Searched refs:Op1Ty (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 1994 auto *Op1Ty = dyn_cast<FixedVectorType>(Op10->getType()); in foldPermuteOfBinops() local
1995 if (!ShuffleDstTy || !BinOpTy || !Op0Ty || !Op1Ty) in foldPermuteOfBinops()
2022 bool IsIdentity1 = ShuffleDstTy == Op1Ty && in foldPermuteOfBinops()
2037 TargetTransformInfo::SK_PermuteTwoSrc, BinOpTy, Op1Ty, Mask1, CostKind, in foldPermuteOfBinops()
2050 Op1Ty, NewMask1, CostKind, 0, nullptr, {Op10, Op11}); in foldPermuteOfBinops()
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| H A D | LoopVectorize.cpp | 5459 Type *Op1Ty = Op1->getOperand(0)->getType(); in getReductionPatternCost() local
5461 Op0Ty->getIntegerBitWidth() < Op1Ty->getIntegerBitWidth() ? Op1Ty in getReductionPatternCost()
5472 Op1->getOpcode(), VectorTy, VectorType::get(Op1Ty, VectorTy), in getReductionPatternCost()
5480 if (Op0Ty != LargestOpTy || Op1Ty != LargestOpTy) { in getReductionPatternCost()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 4167 Type *Op1Ty = IC.getOperand(1)->getType(); in visitICmpInst() local
4168 Check(Op0Ty == Op1Ty, in visitICmpInst()
4182 Type *Op1Ty = FC.getOperand(1)->getType(); in visitFCmpInst() local
4183 Check(Op0Ty == Op1Ty, in visitFCmpInst()
6372 VectorType *Op1Ty = dyn_cast<VectorType>(Op1->getType()); in visitIntrinsicCall() local
6376 Check(Op1Ty && Op2Ty && MaskTy, "Operands must be vectors.", &Call); in visitIntrinsicCall()
6379 Check(Op1Ty->getElementType()->isIntegerTy(), in visitIntrinsicCall()
6381 Check(Op1Ty->getElementType() == Op2Ty->getElementType(), in visitIntrinsicCall()
6383 Check(Op1Ty->getElementCount() == MaskTy->getElementCount(), in visitIntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 1224 const LLT Op0Ty, const LLT Op1Ty) { in validateSelectOp() argument
1228 assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch"); in validateSelectOp()
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| H A D | LegalizerHelper.cpp | 9416 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] = in lowerSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 4630 const LLT Op1Ty = MRI.getType(Op1); in emitVectorConcat() local
4633 if (Op1Ty != Op2Ty) { in emitVectorConcat()
4637 assert(Op1Ty.isVector() && "Expected a vector for vector concat"); in emitVectorConcat()
4639 if (Op1Ty.getSizeInBits() >= 128) { in emitVectorConcat()
4645 if (Op1Ty.getSizeInBits() != 64) { in emitVectorConcat()
4650 const LLT ScalarTy = LLT::scalar(Op1Ty.getSizeInBits()); in emitVectorConcat()
4653 getRegClassForTypeOnBank(Op1Ty.multiplyElements(2), FPRBank); in emitVectorConcat()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 250 const LLT Op1Ty);
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