| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CmovConversion.cpp | 834 Register Op1Reg = MIIt->getOperand(1).getReg(); in convertCmovInstsToBranches() local
841 std::swap(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
843 auto Op1Itr = RegRewriteTable.find(Op1Reg); in convertCmovInstsToBranches()
845 Op1Reg = Op1Itr->second.first; in convertCmovInstsToBranches()
855 .addReg(Op1Reg) in convertCmovInstsToBranches()
869 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
|
| H A D | X86InstructionSelector.cpp | |
| H A D | X86FastISel.cpp | 1427 Register Op1Reg = getRegForValue(Op1); in X86FastEmitCompare() local
1428 if (!Op1Reg) in X86FastEmitCompare()
1432 .addReg(Op1Reg); in X86FastEmitCompare()
1844 Register Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectShift() local
1845 if (!Op1Reg) in X86SelectShift()
1848 CReg).addReg(Op1Reg); in X86SelectShift()
1954 Register Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectDivRem() local
1955 if (!Op1Reg) in X86SelectDivRem()
1991 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()
|
| H A D | X86ISelLowering.cpp | 36159 Register Op1Reg = MIIt->getOperand(1).getReg(); in createPHIsForCMOVsInSinkBB() local
36166 std::swap(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
36168 if (auto It = RegRewriteTable.find(Op1Reg); It != RegRewriteTable.end()) in createPHIsForCMOVsInSinkBB()
36169 Op1Reg = It->second.first; in createPHIsForCMOVsInSinkBB()
36176 .addReg(Op1Reg) in createPHIsForCMOVsInSinkBB()
36182 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
36322 Register Op1Reg = FirstCMOV.getOperand(1).getReg(); in EmitLoweredCascadedSelect() local
36326 .addReg(Op1Reg) in EmitLoweredCascadedSelect()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 252 Register emitLSL_rr(MVT RetVT, Register Op0Reg, Register Op1Reg);
255 Register emitLSR_rr(MVT RetVT, Register Op0Reg, Register Op1Reg);
258 Register emitASR_rr(MVT RetVT, Register Op0Reg, Register Op1Reg);
4082 Register Op1Reg) { in emitLSL_rr() argument
4098 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitLSL_rr()
4100 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg); in emitLSL_rr()
4185 Register Op1Reg) { in emitLSR_rr() argument
4202 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitLSR_rr()
4204 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg); in emitLSR_rr()
4302 Register Op1Reg) { in emitASR_rr() argument
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1169 const Register Op1Reg = I.getOperand(3).getReg(); in selectUAddSub() local
1250 .addReg(Op1Reg); in selectUAddSub()
1658 const Register Op1Reg = I.getOperand(1).getReg(); in selectMulDivRem() local
1662 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectMulDivRem()
1787 if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || in selectMulDivRem()
1798 .addReg(Op1Reg); in selectMulDivRem()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1668 Register Op1Reg = getRegForValue(I->getOperand(1)); in SelectSelect() local
1669 if (!Op1Reg) in SelectSelect()
1716 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); in SelectSelect()
1720 .addReg(Op1Reg) in SelectSelect()
1724 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); in SelectSelect()
1727 .addReg(Op1Reg) in SelectSelect()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 3272 Register Op1Reg = MIIt->getOperand(1).getReg(); in EmitLoweredSelect() local
3279 std::swap(Op1Reg, Op2Reg); in EmitLoweredSelect()
3281 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end()) in EmitLoweredSelect()
3282 Op1Reg = RegRewriteTable[Op1Reg].first; in EmitLoweredSelect()
3289 .addReg(Op1Reg) in EmitLoweredSelect()
3295 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in EmitLoweredSelect()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 2020 Register Op1Reg = getRegForValue(I->getOperand(1)); in selectShift() local
2021 if (!Op1Reg) in selectShift()
2038 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 3870 Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg(); in findCommutedOpIndices() local
3875 if (Op1Reg != MI.getOperand(2).getReg()) in findCommutedOpIndices()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 9416 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] = in lowerSelect()
9423 Op1Reg = MIRBuilder.buildPtrToInt(NewTy, Op1Reg).getReg(0); in lowerSelect()
9460 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
|