| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CmovConversion.cpp | 837 Register Op1Reg = MIIt->getOperand(1).getReg(); in convertCmovInstsToBranches() local
844 std::swap(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
846 auto Op1Itr = RegRewriteTable.find(Op1Reg); in convertCmovInstsToBranches()
848 Op1Reg = Op1Itr->second.first; in convertCmovInstsToBranches()
858 .addReg(Op1Reg) in convertCmovInstsToBranches()
872 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
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| H A D | X86InstructionSelector.cpp | |
| H A D | X86FastISel.cpp | 1427 Register Op1Reg = getRegForValue(Op1); in X86FastEmitCompare() local
1428 if (Op1Reg == 0) return false; in X86FastEmitCompare()
1431 .addReg(Op1Reg); in X86FastEmitCompare()
1839 Register Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectShift() local
1840 if (Op1Reg == 0) return false; in X86SelectShift()
1842 CReg).addReg(Op1Reg); in X86SelectShift()
1948 Register Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectDivRem() local
1949 if (Op1Reg == 0) in X86SelectDivRem()
1985 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()
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| H A D | X86ISelLowering.cpp | 34905 Register Op1Reg = MIIt->getOperand(1).getReg(); in createPHIsForCMOVsInSinkBB() local
34912 std::swap(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
34914 if (RegRewriteTable.contains(Op1Reg)) in createPHIsForCMOVsInSinkBB()
34915 Op1Reg = RegRewriteTable[Op1Reg].first; in createPHIsForCMOVsInSinkBB()
34922 .addReg(Op1Reg) in createPHIsForCMOVsInSinkBB()
34928 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
35068 Register Op1Reg = FirstCMOV.getOperand(1).getReg(); in EmitLoweredCascadedSelect() local
35072 .addReg(Op1Reg) in EmitLoweredCascadedSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 258 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
261 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
264 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
4082 unsigned Op1Reg) { in emitLSL_rr() argument
4097 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitLSL_rr()
4099 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg); in emitLSL_rr()
4184 unsigned Op1Reg) { in emitLSR_rr() argument
4200 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitLSR_rr()
4202 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg); in emitLSR_rr()
4300 unsigned Op1Reg) { in emitASR_rr() argument
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1129 const Register Op1Reg = I.getOperand(3).getReg(); in selectUAddSub() local
1210 .addReg(Op1Reg); in selectUAddSub()
1618 const Register Op1Reg = I.getOperand(1).getReg(); in selectMulDivRem() local
1622 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectMulDivRem()
1747 if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || in selectMulDivRem()
1758 .addReg(Op1Reg); in selectMulDivRem()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1612 Register Op1Reg = getRegForValue(I->getOperand(1)); in SelectSelect() local
1613 if (Op1Reg == 0) return false; in SelectSelect()
1658 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); in SelectSelect()
1662 .addReg(Op1Reg) in SelectSelect()
1666 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); in SelectSelect()
1669 .addReg(Op1Reg) in SelectSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 3272 Register Op1Reg = MIIt->getOperand(1).getReg(); in EmitLoweredSelect() local
3279 std::swap(Op1Reg, Op2Reg); in EmitLoweredSelect()
3281 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end()) in EmitLoweredSelect()
3282 Op1Reg = RegRewriteTable[Op1Reg].first; in EmitLoweredSelect()
3289 .addReg(Op1Reg) in EmitLoweredSelect()
3295 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in EmitLoweredSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 2005 Register Op1Reg = getRegForValue(I->getOperand(1)); in selectShift() local
2006 if (!Op1Reg) in selectShift()
2023 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 3255 Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg(); in findCommutedOpIndices()
3260 if (Op1Reg != MI.getOperand(2).getReg()) in findCommutedOpIndices()
3248 Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg(); findCommutedOpIndices() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 8470 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] = in lowerSelect()
8477 Op1Reg = MIRBuilder.buildPtrToInt(NewTy, Op1Reg).getReg(0); in lowerSelect()
8514 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
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