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Searched refs:Op1Lo (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1410 SDValue Op1Lo, Op1Hi; in SplitVecRes_TernaryOp()
1411 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi); in SplitVecRes_TernaryOp()
1419 Lo = DAG.getNode(Opcode, dl, Op0Lo.getValueType(), Op0Lo, Op1Lo, Op2Lo, Flags); in SplitVecRes_TernaryOp()
1435 {Op0Lo, Op1Lo, Op2Lo, MaskLo, EVLLo}, Flags);
3082 SDValue Op0Lo, Op0Hi, Op1Lo, Op1Hi; in SplitVecRes_VECTOR_DEINTERLEAVE()
3084 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi); in SplitVecRes_VECTOR_DEINTERLEAVE()
3090 DAG.getVTList(VT, VT), Op1Lo, Op1Hi); in SplitVecRes_VECTOR_DEINTERLEAVE()
3097 SDValue Op0Lo, Op0Hi, Op1Lo, Op1Hi; in SplitVecRes_VECTOR_INTERLEAVE()
3099 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi); in SplitVecRes_VECTOR_INTERLEAVE()
3103 DAG.getVTList(VT, VT), Op0Lo, Op1Lo), in SplitVecRes_VECTOR_INTERLEAVE()
1406 SDValue Op1Lo, Op1Hi; SplitVecRes_TernaryOp() local
3078 SDValue Op0Lo, Op0Hi, Op1Lo, Op1Hi; SplitVecRes_VECTOR_DEINTERLEAVE() local
3093 SDValue Op0Lo, Op0Hi, Op1Lo, Op1Hi; SplitVecRes_VECTOR_INTERLEAVE() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp10466 auto [Op1Lo, Op1Hi] = DAG.SplitVectorOperand(Op.getNode(), 1); in lowerVECTOR_DEINTERLEAVE()
10472 DAG.getVTList(SplitVT, SplitVT), Op1Lo, Op1Hi); in lowerVECTOR_DEINTERLEAVE()
10544 auto [Op1Lo, Op1Hi] = DAG.SplitVectorOperand(Op.getNode(), 1); in lowerVECTOR_INTERLEAVE()
10548 DAG.getVTList(SplitVT, SplitVT), Op0Lo, Op1Lo); in lowerVECTOR_INTERLEAVE()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14724 SDValue Op1Lo = DAG.getNode(UnpkLo, dl, WidenedVT, Op.getOperand(1)); in LowerDIV() local
14727 SDValue ResultLo = DAG.getNode(Op.getOpcode(), dl, WidenedVT, Op0Lo, Op1Lo); in LowerDIV()