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Searched refs:Op1L (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp2589 Register Op1L = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in applyMappingImpl() local
2590 MRI.setRegClass(Op1L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2591 MRI.setType(Op1L, S32); in applyMappingImpl()
2592 B.buildTrunc(Op1L, SrcReg1); in applyMappingImpl()
2603 B.buildInstr(NewOpc, {DstReg, CarryOut}, {Op0L, Op1L, Zero64}); in applyMappingImpl()
H A DSIInstrInfo.cpp7867 MachineOperand Op1L = in splitScalarSMulU64() local
7892 .add(Op1L) in splitScalarSMulU64()
7904 .add(Op1L) in splitScalarSMulU64()
7909 .add(Op1L) in splitScalarSMulU64()
7976 MachineOperand Op1L = in splitScalarSMulPseudo() local
7984 BuildMI(MBB, MII, DL, get(NewOpc), DestSub1).add(Op1L).add(Op0L); in splitScalarSMulPseudo()
7988 .add(Op1L) in splitScalarSMulPseudo()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp55457 SDValue Op0L = Op0->getOperand(i), Op1L = Op1->getOperand(i), in matchPMADDWD() local
55461 Op1L.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in matchPMADDWD()
55466 auto *Const1L = dyn_cast<ConstantSDNode>(Op1L->getOperand(1)); in matchPMADDWD()
55496 if (Mul != Op0L->getOperand(0) || Mul != Op1L->getOperand(0) || in matchPMADDWD()