Searched refs:Op0L (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 2583 Register Op0L = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in applyMappingImpl() local
2584 MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2585 MRI.setType(Op0L, S32); in applyMappingImpl()
2586 B.buildTrunc(Op0L, SrcReg0); in applyMappingImpl()
2603 B.buildInstr(NewOpc, {DstReg, CarryOut}, {Op0L, Op1L, Zero64}); in applyMappingImpl()
|
| H A D | SIInstrInfo.cpp | 7865 MachineOperand Op0L = in splitScalarSMulU64() local
7899 .add(Op0L); in splitScalarSMulU64()
7905 .add(Op0L); in splitScalarSMulU64()
7910 .add(Op0L); in splitScalarSMulU64()
7974 MachineOperand Op0L = in splitScalarSMulPseudo() local
7984 BuildMI(MBB, MII, DL, get(NewOpc), DestSub1).add(Op1L).add(Op0L); in splitScalarSMulPseudo()
7989 .add(Op0L); in splitScalarSMulPseudo()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 55457 SDValue Op0L = Op0->getOperand(i), Op1L = Op1->getOperand(i), in matchPMADDWD() local
55460 if (Op0L.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in matchPMADDWD()
55465 auto *Const0L = dyn_cast<ConstantSDNode>(Op0L->getOperand(1)); in matchPMADDWD()
55490 Mul = Op0L->getOperand(0); in matchPMADDWD()
55496 if (Mul != Op0L->getOperand(0) || Mul != Op1L->getOperand(0) || in matchPMADDWD()
|