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Searched refs:Op0L (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp2633 Register Op0L = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in applyMappingImpl() local
2634 MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2635 MRI.setType(Op0L, S32); in applyMappingImpl()
2636 B.buildTrunc(Op0L, SrcReg0); in applyMappingImpl()
2653 B.buildInstr(NewOpc, {DstReg, CarryOut}, {Op0L, Op1L, Zero64}); in applyMappingImpl()
H A DSIInstrInfo.cpp8356 MachineOperand Op0L = in splitScalarSMulU64() local
8390 .add(Op0L); in splitScalarSMulU64()
8396 .add(Op0L); in splitScalarSMulU64()
8401 .add(Op0L); in splitScalarSMulU64()
8465 MachineOperand Op0L = in splitScalarSMulPseudo() local
8475 BuildMI(MBB, MII, DL, get(NewOpc), DestSub1).add(Op1L).add(Op0L); in splitScalarSMulPseudo()
8480 .add(Op0L); in splitScalarSMulPseudo()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp57587 SDValue Op0L = Op0->getOperand(i), Op1L = Op1->getOperand(i), in matchPMADDWD() local
57592 if (!sd_match(Op0L, m_ExtractElt(m_Value(Vec0L), m_ConstInt(Idx0L))) || in matchPMADDWD()