Searched refs:OneRegVT (Results 1 – 1 of 1) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4077 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerBUILD_VECTOR()
4078 MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget); in lowerBUILD_VECTOR()
4091 DAG.getNode(ISD::BUILD_VECTOR, DL, OneRegVT, OneVRegOfOps); in lowerBUILD_VECTOR()
5050 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerShuffleViaVRegSplitting()
5051 MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget); in lowerShuffleViaVRegSplitting()
5068 SubVec = convertFromScalableVector(OneRegVT, SubVec, DAG, Subtarget); in lowerShuffleViaVRegSplitting()
5069 SubVec = DAG.getVectorShuffle(OneRegVT, DL, SubVec, SubVec, SrcSubMask); in lowerShuffleViaVRegSplitting()
4076 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); lowerBUILD_VECTOR() local
5049 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); lowerShuffleViaVRegSplitting() local
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