| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 203 int64_t Offset1 = 0; in getHazardType() local
209 Ptr1 = GetPointerBaseWithConstantOffset(BaseVal1, Offset1, DL, true); in getHazardType()
211 return CheckOffsets(Offset0, Offset1); in getHazardType()
221 Offset1 = MF.getFrameInfo().getObjectOffset(FS1->getFrameIndex()); in getHazardType()
222 return CheckOffsets(Offset0, Offset1); in getHazardType()
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| H A D | ARMBaseInstrInfo.h | 249 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
261 int64_t Offset1, int64_t Offset2,
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| H A D | ARMBaseInstrInfo.cpp | 1792 int64_t &Offset1, in areLoadsFromSameBasePtr() argument
1839 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
1859 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
1864 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
1866 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.h | 125 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
136 SDValue &Offset1) const;
138 SDValue &Offset1) const;
140 SDValue &Offset1, unsigned Size) const;
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| H A D | AMDGPUISelDAGToDAG.cpp | 1267 unsigned Offset1, in isDSOffset2Legal() argument
1269 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
1271 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
1361 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned()
1362 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4); in SelectDS64Bit4ByteAligned()
1367 SDValue &Offset1) const { in SelectDS128Bit8ByteAligned()
1368 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 8); in SelectDS128Bit8ByteAligned()
1372 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2() argument
1387 Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i32); in SelectDSReadWrite2()
1424 Offset1 = in SelectDSReadWrite2()
[all …]
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| H A D | SIInstrInfo.h | 247 int64_t &Offset1) const override;
258 int64_t Offset1, bool OffsetIsScalable1,
265 int64_t Offset1, unsigned NumLoads) const override;
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| H A D | AMDGPUInstructionSelector.h | 266 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
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| H A D | SIInstrInfo.cpp | 238 int64_t &Offset1) const { in areLoadsFromSameBasePtr()
278 Offset1 = Load1->getConstantOperandVal(Offset1Idx); in areLoadsFromSameBasePtr()
310 Offset1 = Load1Offset->getZExtValue(); in areLoadsFromSameBasePtr()
343 Offset1 = Off1->getAsZExtVal(); in areLoadsFromSameBasePtr()
404 unsigned Offset1 = Offset1Op->getImm() & 0xff; in getMemOperandsWithOffsetWidth() local
405 if (Offset0 + 1 != Offset1) in getMemOperandsWithOffsetWidth()
560 int64_t Offset1, bool OffsetIsScalable1, in shouldClusterMemOps() argument
612 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
614 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
620 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
[all …]
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| H A D | AMDGPUInstructionSelector.cpp | 1803 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (Instruction << 4); in selectDSOrderedIntrinsic() local
1806 Offset1 |= (CountDw - 1) << 6; in selectDSOrderedIntrinsic()
1809 Offset1 |= ShaderType << 2; in selectDSOrderedIntrinsic()
1811 unsigned Offset = Offset0 | (Offset1 << 8); in selectDSOrderedIntrinsic()
5735 int64_t Offset1, in isDSOffset2Legal() argument
5737 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
5739 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
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| H A D | DSInstructions.td | 169 Offset0:$offset0, Offset1:$offset1, gds:$gds),
254 (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, Offset0:$offset0, Offset1:$offset1, gds:$gds),
330 (ins VGPR_32:$addr, Offset0:$offset0, Offset1:$offset1, gds:$gds),
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 684 APInt Offset1(DL.getIndexTypeSizeInBits(Load1Ptr->getType()), 0); in foldLoadsRecursive() local
686 Load1Ptr->stripAndAccumulateConstantOffsets(DL, Offset1, in foldLoadsRecursive()
728 if (Offset2.slt(Offset1)) { in foldLoadsRecursive()
731 std::swap(Offset1, Offset2); in foldLoadsRecursive()
762 if ((Shift2 - Shift1) != ShiftDiff || (Offset2 - Offset1) != PrevSize) in foldLoadsRecursive()
818 APInt Offset1(DL.getIndexTypeSizeInBits(Load1Ptr->getType()), 0); in foldConsecutiveLoads() local
820 DL, Offset1, /* AllowNonInbounds */ true); in foldConsecutiveLoads()
821 Load1Ptr = Builder.CreatePtrAdd(Load1Ptr, Builder.getInt(Offset1)); in foldConsecutiveLoads()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 247 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
248 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
249 Offset1 == Offset2 || in ClusterNeighboringLoads()
255 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
256 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
259 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 408 int64_t Offset1; in apply() local
410 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply()
416 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 400 int64_t Offset1, Offset2; in ConsecutiveInstr() local
401 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Value.cpp | 1060 APInt Offset1(DL.getIndexTypeSizeInBits(Ptr1->getType()), 0); in getPointerOffsetFrom() local
1062 Ptr1 = Ptr1->stripAndAccumulateConstantOffsets(DL, Offset1, true); in getPointerOffsetFrom()
1067 return Offset2.getSExtValue() - Offset1.getSExtValue(); in getPointerOffsetFrom()
1092 Offset1.getSExtValue(); in getPointerOffsetFrom()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 524 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
542 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | ContainerModeling.cpp | 130 SymbolRef Offset1,
973 SymbolRef Offset1, in invalidateIteratorPositions() argument
978 return compare(State, Pos.getOffset(), Offset1, Opc1) && in invalidateIteratorPositions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1511 int64_t &Offset1, in areLoadsFromSameBasePtr() argument
1525 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
1628 int64_t Offset1, bool OffsetIsScalable1, in shouldClusterMemOps() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 179 int64_t Offset1, bool OffsetIsScalable1,
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | SeparateConstOffsetFromGEP.cpp | 1434 Value *Offset1 = First->getOperand(1); in swapGEPOperand() local
1437 Second->setOperand(1, Offset1); in swapGEPOperand()
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| H A D | ConstraintElimination.cpp | 724 int64_t Offset1 = ADec.Offset; in getConstraint() local
726 Offset1 *= -1; in getConstraint()
776 if (AddOverflow(Offset1, Offset2, OffsetSum)) in getConstraint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 686 int64_t Offset1, bool OffsetIsScalable1,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 331 int64_t Offset1, bool OffsetIsScalable1,
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| H A D | AArch64InstrInfo.cpp | 4868 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument
4885 ObjectOffset1 += Offset1; in shouldClusterFI()
4936 int64_t Offset1 = FirstLdSt.getOperand(2).getImm(); in shouldClusterMemOps() local
4937 if (hasUnscaledLdStOffset(FirstOpc) && !scaleOffset(FirstOpc, Offset1)) in shouldClusterMemOps()
4945 if (Offset1 > 63 || Offset1 < -64) in shouldClusterMemOps()
4951 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
4956 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
4960 assert(Offset1 <= Offset2 && "Caller should have ordered offsets."); in shouldClusterMemOps()
4962 return Offset1 + 1 == Offset2; in shouldClusterMemOps()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 1016 int64_t Offset1, Offset2; in hasLoopCarriedMemDep() local
1018 if (TII->getMemOperandWithOffset(SrcMI, BaseOp1, Offset1, Offset1IsScalable, in hasLoopCarriedMemDep()
1024 (int)Offset1 < (int)Offset2) { in hasLoopCarriedMemDep()
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