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Searched refs:Offset0 (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp192 int64_t Offset0 = 0; in getHazardType() local
210 Ptr0 = GetPointerBaseWithConstantOffset(BaseVal0, Offset0, DL, true); in getHazardType()
213 return CheckOffsets(Offset0, Offset1); in getHazardType()
222 Offset0 = MF.getFrameInfo().getObjectOffset(FS0->getFrameIndex()); in getHazardType()
224 return CheckOffsets(Offset0, Offset1); in getHazardType()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h129 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
139 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
141 bool SelectDS128Bit8ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
143 bool SelectDSReadWrite2(SDValue Ptr, SDValue &Base, SDValue &Offset0,
H A DAMDGPUISelDAGToDAG.cpp1153 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0, in isDSOffset2Legal() argument
1156 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
1158 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
1247 SDValue &Offset0, in SelectDS64Bit4ByteAligned() argument
1249 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4); in SelectDS64Bit4ByteAligned()
1253 SDValue &Offset0, in SelectDS128Bit8ByteAligned() argument
1255 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 8); in SelectDS128Bit8ByteAligned()
1259 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2() argument
1273 Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8); in SelectDSReadWrite2()
1309 Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8); in SelectDSReadWrite2()
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H A DAMDGPUInstructionSelector.h258 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
H A DSIInstrInfo.h237 bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
253 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
H A DSIInstrInfo.cpp231 int64_t &Offset0, in areLoadsFromSameBasePtr() argument
271 Offset0 = Load0->getConstantOperandVal(Offset0Idx); in areLoadsFromSameBasePtr()
303 Offset0 = Load0Offset->getZExtValue(); in areLoadsFromSameBasePtr()
336 Offset0 = Off0->getAsZExtVal(); in areLoadsFromSameBasePtr()
394 unsigned Offset0 = Offset0Op->getImm() & 0xff; in getMemOperandsWithOffsetWidth() local
396 if (Offset0 + 1 != Offset1) in getMemOperandsWithOffsetWidth()
415 Offset = EltSize * Offset0; in getMemOperandsWithOffsetWidth()
595 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
597 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
603 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
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H A DDSInstructions.td159 Offset0:$offset0, Offset1:$offset1, gds:$gds),
246 (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, Offset0:$offset0, Offset1:$offset1, gds:$gds),
305 (ins VGPR_32:$addr, Offset0:$offset0, Offset1:$offset1, gds:$gds),
H A DAMDGPUInstructionSelector.cpp1587 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
1596 unsigned Offset = Offset0 | (Offset1 << 8); in selectDSOrderedIntrinsic()
4700 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, in isDSOffset2Legal() argument
4703 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
4705 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
H A DSIInstrInfo.td1070 def Offset0 : NamedIntOperand<i8, "offset0">;
H A DSIISelLowering.cpp8877 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
8886 unsigned Offset = Offset0 | (Offset1 << 8); in LowerINTRINSIC_W_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp393 int64_t Offset0; in apply() local
395 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0); in apply()
415 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
H A DHexagonISelLoweringHVX.cpp2196 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp()
2200 {Mask, Base, Offset0, Value, Chain}, DAG); in LowerHvxMaskedOp()
2227 {MaskU.first, Base, Offset0, ValueU.first, Chain}, DAG); in LowerHvxMaskedOp()
2197 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); LowerHvxMaskedOp() local
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DConstantFolding.cpp1249 APInt Offset0(IndexWidth, 0); in ConstantFoldCompareInstOperands() local
1251 Ops0->stripAndAccumulateInBoundsConstantOffsets(DL, Offset0); in ConstantFoldCompareInstOperands()
1258 ICmpInst::compare(Offset0, Offset1, in ConstantFoldCompareInstOperands()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp18631 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
18640 APInt CNV = Offset0; in CombineToPreIndexedLoadStore()
20914 int64_t Offset0 = LoadNodes[0].OffsetFromBase; in tryStoreMergeOfLoads() local
20917 if (Offset0 - Offset1 == ElementSizeBytes && in tryStoreMergeOfLoads()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6096 bool Offset0 = false, Offset1 = false; in getFauxShuffleMask() local
6108 Offset0 = true; in getFauxShuffleMask()
6133 if (Offset0 || Offset1) { in getFauxShuffleMask()
6135 if ((Offset0 && isInRange(M, 0, NumElts)) || in getFauxShuffleMask()