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Searched refs:OPW64 (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td1139 def SSrc_b64 : SrcRegOrImm9 <SReg_64, "OPW64", "OPERAND_REG_IMM_INT64", 64, OperandSemantics.INT>;
1162 def SCSrc_b64 : SrcRegOrImm9 <SReg_64, "OPW64", "OPERAND_REG_INLINE_C_INT64", 64, OperandSemantics.…
1212 def VSrc_b64 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_INT64", 64, OperandSemantics.INT>;
1213 def VSrc_f64 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_FP64", 64, OperandSemantics.FP64> {
1216 def VSrc_v2b32 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_V2INT32", 32, OperandSemantics.INT>;
1217 def VSrc_v2f32 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_V2FP32", 32, OperandSemantics.FP32>;
1244 def VRegSrc_64 : SrcReg9<VReg_64, "OPW64">;
1306 def VISrc_64_bf16 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_BF16", 16, OperandSemanti…
1307 def VISrc_64_f16 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_FP16", 16, OperandSemantic…
1308 def VISrc_64_b32 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemanti…
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp294 DECODE_OPERAND_REG_7(SReg_64, OPW64) in DECODE_OPERAND_REG_8()
295 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) in DECODE_OPERAND_REG_8()
437 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, in decodeOperand_VSrc_f64()
1424 case OPW64: in getVgprClassId()
1449 case OPW64: in getAgprClassId()
1475 case OPW64: in getSgprClassId()
1499 case OPW64: in getTtmpClassId()
1577 case OPW64: in decodeNonVGPRSrcOp()
1731 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); in decodeSDWAVopcDst()
1737 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); in decodeSDWAVopcDst()
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H A DAMDGPUDisassembler.h217 OPW64, enumerator