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Searched refs:NumSubRegs (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp83 unsigned NumSubRegs; member
127 NumSubRegs = SplitParts.empty() ? 1 : SplitParts.size(); in SGPRSpillBuilder()
147 Data.NumVGPRs = (NumSubRegs + (Data.PerVGPR - 1)) / Data.PerVGPR; in getPerVGPRData()
148 Data.VGPRLanes = (1LL << std::min(Data.PerVGPR, NumSubRegs)) - 1LL; in getPerVGPRData()
1357 unsigned NumSubRegs = RegWidth / EltSize; in buildSpillLoadStore() local
1358 unsigned Size = NumSubRegs * EltSize; in buildSpillLoadStore()
1517 for (unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e; in buildSpillLoadStore()
1519 if (i == NumSubRegs) { in buildSpillLoadStore()
1778 assert(SB.NumSubRegs == VGPRSpills.size() && in spillSGPR()
1781 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) { in spillSGPR()
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H A DSIFrameLowering.cpp239 unsigned NumSubRegs; member in llvm::PrologEpilogSGPRSpillBuilder
253 for (unsigned I = 0, DwordOff = 0; I < NumSubRegs; ++I) { in saveToMemory()
254 Register SubReg = NumSubRegs == 1 in saveToMemory()
272 assert(Spill.size() == NumSubRegs); in saveToVGPRLane()
274 for (unsigned I = 0; I < NumSubRegs; ++I) { in saveToVGPRLane()
275 Register SubReg = NumSubRegs == 1 in saveToVGPRLane()
301 for (unsigned I = 0, DwordOff = 0; I < NumSubRegs; ++I) { in restoreFromMemory()
302 Register SubReg = NumSubRegs == 1 in restoreFromMemory()
318 assert(Spill.size() == NumSubRegs); in restoreFromVGPRLane()
320 for (unsigned I = 0; I < NumSubRegs; ++I) { in restoreFromVGPRLane()
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H A DSIInstrInfo.cpp6285 unsigned NumSubRegs = RegSize / 32; in emitLoadScalarOpsFromVGPRLoop() local
6288 if (NumSubRegs == 1) { in emitLoadScalarOpsFromVGPRLoop()
6316 assert(NumSubRegs % 2 == 0 && NumSubRegs <= 32 && in emitLoadScalarOpsFromVGPRLoop()
6319 for (unsigned Idx = 0; Idx < NumSubRegs; Idx += 2) { in emitLoadScalarOpsFromVGPRLoop()
6347 if (NumSubRegs <= 2) in emitLoadScalarOpsFromVGPRLoop()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp329 const MCInstrDesc &MCID, unsigned int NumSubRegs, in copyPhysSubRegs() argument
334 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) { in copyPhysSubRegs()
394 unsigned int NumSubRegs = 2; in copyPhysReg() local
396 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
400 unsigned int NumSubRegs = 2; in copyPhysReg() local
402 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp28683 unsigned NumSubRegs = RegisterVT.getFixedSizeInBits() / 128; in getVectorTypeBreakdownForCallingConv() local
28684 NumIntermediates *= NumSubRegs; in getVectorTypeBreakdownForCallingConv()
28685 NumRegs *= NumSubRegs; in getVectorTypeBreakdownForCallingConv()