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Searched refs:NumSubElts (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h1359 int NumSubElts, SubIndex; in getInstructionCost() local
1372 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex)) in getInstructionCost()
1375 FixedVectorType::get(VecTy->getScalarType(), NumSubElts), in getInstructionCost()
1391 NumSubElts = VecSrcTy->getElementCount().getKnownMinValue(); in getInstructionCost()
1399 M = M >= NumSubElts ? (M + (Mask.size() - NumSubElts)) : M; in getInstructionCost()
1408 AdjustMask.append(NumSubElts - Mask.size(), PoisonMaskElem); in getInstructionCost()
1447 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex)) in getInstructionCost()
1450 FixedVectorType::get(VecTy->getScalarType(), NumSubElts), Operands, in getInstructionCost()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h135 int NumSubElts = SubVTy->getNumElements(); in getExtractSubvectorOverhead() local
137 (Index + NumSubElts) <= in getExtractSubvectorOverhead()
145 for (int i = 0; i != NumSubElts; ++i) { in getExtractSubvectorOverhead()
163 int NumSubElts = SubVTy->getNumElements(); in getInsertSubvectorOverhead() local
165 (Index + NumSubElts) <= in getInsertSubvectorOverhead()
173 for (int i = 0; i != NumSubElts; ++i) { in getInsertSubvectorOverhead()
995 int NumSubElts; in improveShuffleKindFromMask() local
997 Mask, NumSrcElts, NumSubElts, Index)) { in improveShuffleKindFromMask()
998 if (Index + NumSubElts > NumSrcElts) in improveShuffleKindFromMask()
1000 SubTy = FixedVectorType::get(Ty->getElementType(), NumSubElts); in improveShuffleKindFromMask()
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/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DInstructions.cpp2039 int NumSrcElts, int &NumSubElts, in isInsertSubvectorMask() argument
2090 NumSubElts = NumSub1Elts; in isInsertSubvectorMask()
2102 NumSubElts = NumSub0Elts; in isInsertSubvectorMask()
2404 static int matchShuffleAsBitRotate(ArrayRef<int> Mask, int NumSubElts) { in matchShuffleAsBitRotate() argument
2406 assert((NumElts % NumSubElts) == 0 && "Illegal shuffle mask"); in matchShuffleAsBitRotate()
2409 for (int i = 0; i != NumElts; i += NumSubElts) { in matchShuffleAsBitRotate()
2410 for (int j = 0; j != NumSubElts; ++j) { in matchShuffleAsBitRotate()
2414 if (M < i || M >= i + NumSubElts) in matchShuffleAsBitRotate()
2416 int Offset = (NumSubElts - (M - (i + j))) % NumSubElts; in matchShuffleAsBitRotate()
2427 unsigned MaxSubElts, unsigned &NumSubElts, unsigned &RotateAmt) { in isBitRotateMask() argument
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp884 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in SimplifyMultipleUseDemandedBits() local
885 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in SimplifyMultipleUseDemandedBits()
1261 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in SimplifyDemandedBits() local
1262 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in SimplifyDemandedBits()
1264 DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); in SimplifyDemandedBits()
1332 unsigned NumSubElts = SubVT.getVectorNumElements(); in SimplifyDemandedBits() local
1335 DemandedElts.extractBits(NumSubElts, i * NumSubElts); in SimplifyDemandedBits()
1428 unsigned NumSubElts = in SimplifyDemandedBits() local
1432 APInt::getBitsSet(NumElts, SubIdx, SubIdx + NumSubElts); in SimplifyDemandedBits()
3275 unsigned NumSubElts = SubVT.getVectorNumElements(); in SimplifyDemandedVectorElts() local
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H A DSelectionDAG.cpp3311 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in computeKnownBits() local
3312 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in computeKnownBits()
3314 DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); in computeKnownBits()
4963 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in ComputeNumSignBits() local
4964 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in ComputeNumSignBits()
4966 DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); in ComputeNumSignBits()
12296 auto PartialReduction = [&](SDValue Op, unsigned NumSubElts) { in matchBinOpReduction() argument
12301 EVT SubVT = EVT::getVectorVT(*getContext(), OpSVT, NumSubElts); in matchBinOpReduction()
H A DDAGCombiner.cpp24802 unsigned NumSubElts = NVT.getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR() local
24803 if (InsIdx <= ExtIdx && (ExtIdx + NumSubElts) <= (InsIdx + NumInsElts) && in visitEXTRACT_SUBVECTOR()
25960 int NumSubElts = SubVT.getVectorNumElements(); in visitVECTOR_SHUFFLE() local
25961 assert((NumElts % NumSubElts) == 0 && "Subvector mismatch"); in visitVECTOR_SHUFFLE()
25973 for (int SubIdx = 0; SubIdx != (int)NumElts; SubIdx += NumSubElts) { in visitVECTOR_SHUFFLE()
25979 InsertionMask.begin() + SubIdx + NumSubElts, in visitVECTOR_SHUFFLE()
25980 NumElts + (SubVec * NumSubElts)); in visitVECTOR_SHUFFLE()
26951 int NumSubElts = NumElts * Split; in XformToShuffleWithZero() local
26955 for (int i = 0; i != NumSubElts; ++i) { in XformToShuffleWithZero()
26962 Indices.push_back(i + NumSubElts); in XformToShuffleWithZero()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstructions.h2150 int &NumSubElts, int &Index);
2152 int &NumSubElts, int &Index) {
2160 return isInsertSubvectorMask(MaskAsInts, NumSrcElts, NumSubElts, Index);
2164 bool isInsertSubvectorMask(int &NumSubElts, int &Index) const {
2172 return isInsertSubvectorMask(ShuffleMask, NumSrcElts, NumSubElts, Index);
2278 unsigned &NumSubElts, unsigned &RotateAmt);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1574 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
1575 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
1584 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && in getShuffleCost()
1585 (NumSubElts % OrigSubElts) == 0 && in getShuffleCost()
1590 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && in getShuffleCost()
1596 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); in getShuffleCost()
1623 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
1624 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
H A DX86InstCombineIntrinsic.cpp266 for (unsigned i = 0, NumSubElts = 64 / BitWidth; i != NumSubElts; ++i) { in simplifyX86immShift() local
267 unsigned SubEltIdx = (NumSubElts - 1) - i; in simplifyX86immShift()
H A DX86ISelLowering.cpp4250 unsigned NumSubElts = OpVT.getVectorNumElements() / NumSubs; in SplitOpsAndApply() local
4252 SubOps.push_back(extractSubVector(Op, i * NumSubElts, DAG, DL, SizeSub)); in SplitOpsAndApply()
4935 unsigned NumSubElts = SubVecSizeInBits / CstEltSizeInBits; in getTargetConstantBitsFromNode() local
4937 APInt UndefSubElts(NumSubElts, 0); in getTargetConstantBitsFromNode()
4938 SmallVector<APInt, 64> SubEltBits(NumSubElts * NumSubVecs, in getTargetConstantBitsFromNode()
4940 for (unsigned i = 0; i != NumSubElts; ++i) { in getTargetConstantBitsFromNode()
4945 SubEltBits[i + (j * NumSubElts)] = SubEltBits[i]; in getTargetConstantBitsFromNode()
5004 unsigned NumSubElts = VT.getVectorNumElements(); in getTargetConstantBitsFromNode() local
5006 UndefElts = UndefElts.extractBits(NumSubElts, BaseIdx); in getTargetConstantBitsFromNode()
5007 if ((BaseIdx + NumSubElts) != NumSrcElts) in getTargetConstantBitsFromNode()
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H A DX86ISelDAGToDAG.cpp1081 unsigned NumSubElts = VT.getSizeInBits() / MaxVT.getScalarSizeInBits(); in PreprocessISelDAG() local
1082 MVT SubVT = MVT::getVectorVT(MaxVT.getScalarType(), NumSubElts); in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19575 unsigned NumSubElts = SubVT.getVectorNumElements(); in performInsertSubvectorCombine() local
19577 (IdxVal != 0 && IdxVal != NumSubElts)) in performInsertSubvectorCombine()
19587 DAG.getVectorIdxConstant(NumSubElts, DL)); in performInsertSubvectorCombine()
20549 int NumSubElts = NumElts / 4; in isLoadOrMultipleLoads() local
20550 for (int I = 0; I < NumSubElts; I++) { in isLoadOrMultipleLoads()
20553 SV1->getMaskElt(I + NumSubElts) != I + NumSubElts || in isLoadOrMultipleLoads()
20554 SV1->getMaskElt(I + NumSubElts * 2) != I + NumSubElts * 2 || in isLoadOrMultipleLoads()
20555 SV1->getMaskElt(I + NumSubElts * 3) != I + NumElts) in isLoadOrMultipleLoads()
20559 SV2->getMaskElt(I + NumSubElts) != I + NumSubElts || in isLoadOrMultipleLoads()
20560 SV2->getMaskElt(I + NumSubElts * 2) != I + NumElts) in isLoadOrMultipleLoads()
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H A DAArch64TargetTransformInfo.cpp4303 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
4304 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4701 int NumSubElts, Index; in lowerVECTOR_SHUFFLEAsVSlideup()
4702 if (!ShuffleVectorInst::isInsertSubvectorMask(Mask, NumElts, NumSubElts, in lowerVECTOR_SHUFFLEAsVSlideup()
4718 if (NumSubElts + Index >= (int)NumElts) in lowerVECTOR_SHUFFLEAsVSlideup()
4723 SDValue VL = DAG.getConstant(NumSubElts + Index, DL, XLenVT); in lowerVECTOR_SHUFFLEAsVSlideup()
4954 unsigned NumSubElts; in isLegalBitRotate()
4956 NumElts, NumSubElts, RotateAmt)) in isLegalBitRotate()
4958 RotateVT = MVT::getVectorVT(MVT::getIntegerVT(EltSizeInBits * NumSubElts), in isLegalBitRotate()
4959 NumElts / NumSubElts); in isLegalBitRotate()
4700 int NumSubElts, Index; lowerVECTOR_SHUFFLEAsVSlideup() local
4953 unsigned NumSubElts; isLegalBitRotate() local
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp8053 int NumSubElts; in getShuffleCost() local
8055 Mask, NumSrcElts, NumSubElts, Index)) { in getShuffleCost()
8056 if (Index + NumSubElts > NumSrcElts && in getShuffleCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp15668 unsigned NumSubElts = SubVT.getVectorNumElements(); in PerformInsertSubvectorCombine() local
15670 (IdxVal != 0 && IdxVal != NumSubElts)) in PerformInsertSubvectorCombine()
15681 DCI.DAG.getVectorIdxConstant(NumSubElts, DL)); in PerformInsertSubvectorCombine()