| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfoImpl.h | 1536 int NumSubElts, SubIndex; in getInstructionCost() local
1553 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex)) in getInstructionCost()
1557 FixedVectorType::get(VecTy->getScalarType(), NumSubElts), in getInstructionCost()
1573 NumSubElts = VecSrcTy->getElementCount().getKnownMinValue(); in getInstructionCost()
1581 M = M >= NumSubElts ? (M + (Mask.size() - NumSubElts)) : M; in getInstructionCost()
1592 AdjustMask.append(NumSubElts - Mask.size(), PoisonMaskElem); in getInstructionCost()
1629 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex)) in getInstructionCost()
1632 FixedVectorType::get(VecTy->getScalarType(), NumSubElts), Operands, in getInstructionCost()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | BasicTTIImpl.h | 137 int NumSubElts = SubVTy->getNumElements(); in getExtractSubvectorOverhead() local
139 (Index + NumSubElts) <= in getExtractSubvectorOverhead()
147 for (int i = 0; i != NumSubElts; ++i) { in getExtractSubvectorOverhead()
165 int NumSubElts = SubVTy->getNumElements(); in getInsertSubvectorOverhead() local
167 (Index + NumSubElts) <= in getInsertSubvectorOverhead()
175 for (int i = 0; i != NumSubElts; ++i) { in getInsertSubvectorOverhead()
1129 int NumSubElts; in improveShuffleKindFromMask() local
1131 Mask, NumSrcElts, NumSubElts, Index)) { in improveShuffleKindFromMask()
1132 if (Index + NumSubElts > NumSrcElts) in improveShuffleKindFromMask()
1134 SubTy = FixedVectorType::get(SrcTy->getElementType(), NumSubElts); in improveShuffleKindFromMask()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Instructions.cpp | 2104 int NumSrcElts, int &NumSubElts, in isInsertSubvectorMask() argument
2155 NumSubElts = NumSub1Elts; in isInsertSubvectorMask()
2167 NumSubElts = NumSub0Elts; in isInsertSubvectorMask()
2469 static int matchShuffleAsBitRotate(ArrayRef<int> Mask, int NumSubElts) { in matchShuffleAsBitRotate() argument
2471 assert((NumElts % NumSubElts) == 0 && "Illegal shuffle mask"); in matchShuffleAsBitRotate()
2474 for (int i = 0; i != NumElts; i += NumSubElts) { in matchShuffleAsBitRotate()
2475 for (int j = 0; j != NumSubElts; ++j) { in matchShuffleAsBitRotate()
2479 if (M < i || M >= i + NumSubElts) in matchShuffleAsBitRotate()
2481 int Offset = (NumSubElts - (M - (i + j))) % NumSubElts; in matchShuffleAsBitRotate()
2492 unsigned MaxSubElts, unsigned &NumSubElts, unsigned &RotateAmt) { in isBitRotateMask() argument
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| /freebsd/contrib/llvm-project/llvm/include/llvm/SandboxIR/ |
| H A D | Instruction.h | 831 int &NumSubElts, int &Index) { in isInsertSubvectorMask() argument
833 NumSubElts, Index); in isInsertSubvectorMask()
836 int &NumSubElts, int &Index) { in isInsertSubvectorMask() argument
838 cast<llvm::Constant>(Mask->Val), NumSrcElts, NumSubElts, Index); in isInsertSubvectorMask()
842 bool isInsertSubvectorMask(int &NumSubElts, int &Index) const { in isInsertSubvectorMask() argument
843 return cast<llvm::ShuffleVectorInst>(Val)->isInsertSubvectorMask(NumSubElts, in isInsertSubvectorMask()
955 unsigned &NumSubElts, unsigned &RotateAmt) { in isBitRotateMask() argument
957 Mask, EltSizeInBits, MinSubElts, MaxSubElts, NumSubElts, RotateAmt); in isBitRotateMask()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 939 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in SimplifyMultipleUseDemandedBits() local
940 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in SimplifyMultipleUseDemandedBits()
1316 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in SimplifyDemandedBits() local
1317 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in SimplifyDemandedBits()
1319 DemandedSrcElts.clearBits(Idx, Idx + NumSubElts); in SimplifyDemandedBits()
1387 unsigned NumSubElts = SubVT.getVectorNumElements(); in SimplifyDemandedBits() local
1390 DemandedElts.extractBits(NumSubElts, i * NumSubElts); in SimplifyDemandedBits()
1483 unsigned NumSubElts = in SimplifyDemandedBits() local
1487 APInt::getBitsSet(NumElts, SubIdx, SubIdx + NumSubElts); in SimplifyDemandedBits()
3416 unsigned NumSubElts = SubVT.getVectorNumElements(); in SimplifyDemandedVectorElts() local
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| H A D | SelectionDAG.cpp | 3554 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in computeKnownBits() local
3555 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in computeKnownBits()
3557 DemandedSrcElts.clearBits(Idx, Idx + NumSubElts); in computeKnownBits()
5238 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in ComputeNumSignBits() local
5239 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in ComputeNumSignBits()
5241 DemandedSrcElts.clearBits(Idx, Idx + NumSubElts); in ComputeNumSignBits()
5853 unsigned NumSubElts = SubVector.getValueType().getVectorNumElements(); in isKnownNeverNaN() local
5858 APInt::getBitsSet(NumBaseElts, Idx, Idx + NumSubElts); in isKnownNeverNaN()
5860 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in isKnownNeverNaN()
12862 auto PartialReduction = [&](SDValue Op, unsigned NumSubElts) { in matchBinOpReduction() argument
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| H A D | DAGCombiner.cpp | 25856 unsigned NumSubElts = NVT.getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR() local
25857 if (InsIdx <= ExtIdx && (ExtIdx + NumSubElts) <= (InsIdx + NumInsElts) && in visitEXTRACT_SUBVECTOR()
26029 unsigned NumSubElts = User->getValueType(0).getVectorNumElements(); in visitEXTRACT_SUBVECTOR() local
26030 DemandedElts.setBits(ExtIdx, ExtIdx + NumSubElts); in visitEXTRACT_SUBVECTOR()
27053 int NumSubElts = SubVT.getVectorNumElements(); in visitVECTOR_SHUFFLE() local
27054 assert((NumElts % NumSubElts) == 0 && "Subvector mismatch"); in visitVECTOR_SHUFFLE()
27066 for (int SubIdx = 0; SubIdx != (int)NumElts; SubIdx += NumSubElts) { in visitVECTOR_SHUFFLE()
27072 InsertionMask.begin() + SubIdx + NumSubElts, in visitVECTOR_SHUFFLE()
27073 NumElts + (SubVec * NumSubElts)); in visitVECTOR_SHUFFLE()
28066 int NumSubElts = NumElts * Split; in XformToShuffleWithZero() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | Instructions.h | 2280 int &NumSubElts, int &Index);
2282 int &NumSubElts, int &Index) {
2290 return isInsertSubvectorMask(MaskAsInts, NumSrcElts, NumSubElts, Index);
2294 bool isInsertSubvectorMask(int &NumSubElts, int &Index) const {
2302 return isInsertSubvectorMask(ShuffleMask, NumSrcElts, NumSubElts, Index);
2410 unsigned &NumSubElts,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 1612 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
1613 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
1622 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && in getShuffleCost()
1623 (NumSubElts % OrigSubElts) == 0 && in getShuffleCost()
1628 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && in getShuffleCost()
1634 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); in getShuffleCost()
1664 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
1666 NumElts == NumSubElts && in getShuffleCost()
1667 (SubTp->getElementCount().getKnownMinValue() % NumSubElts) == 0; in getShuffleCost()
1668 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
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| H A D | X86InstCombineIntrinsic.cpp | 260 for (unsigned i = 0, NumSubElts = 64 / BitWidth; i != NumSubElts; ++i) { in simplifyX86immShift() local
261 unsigned SubEltIdx = (NumSubElts - 1) - i; in simplifyX86immShift()
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| H A D | X86ISelLowering.cpp | 4482 unsigned NumSubElts = OpVT.getVectorNumElements() / NumSubs; in SplitOpsAndApply() local
4484 SubOps.push_back(extractSubVector(Op, i * NumSubElts, DAG, DL, SizeSub)); in SplitOpsAndApply()
5195 unsigned NumSubElts = SubVecSizeInBits / CstEltSizeInBits; in getTargetConstantBitsFromNode() local
5197 APInt UndefSubElts(NumSubElts, 0); in getTargetConstantBitsFromNode()
5198 SmallVector<APInt, 64> SubEltBits(NumSubElts * NumSubVecs, in getTargetConstantBitsFromNode()
5200 for (unsigned i = 0; i != NumSubElts; ++i) { in getTargetConstantBitsFromNode()
5205 SubEltBits[i + (j * NumSubElts)] = SubEltBits[i]; in getTargetConstantBitsFromNode()
5260 unsigned NumSubElts = VT.getSizeInBits() / EltSizeInBits; in getTargetConstantBitsFromNode() local
5267 UndefElts = UndefElts.extractBits(NumSubElts, BaseIdx); in getTargetConstantBitsFromNode()
5268 if ((BaseIdx + NumSubElts) != NumSrcElts) in getTargetConstantBitsFromNode()
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| H A D | X86ISelDAGToDAG.cpp | 1125 unsigned NumSubElts = VT.getSizeInBits() / MaxVT.getScalarSizeInBits(); in PreprocessISelDAG() local
1126 MVT SubVT = MVT::getVectorVT(MaxVT.getScalarType(), NumSubElts); in PreprocessISelDAG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 20286 unsigned NumSubElts = SubVT.getVectorNumElements(); in performInsertSubvectorCombine() local
20288 (IdxVal != 0 && IdxVal != NumSubElts)) in performInsertSubvectorCombine()
20298 DAG.getVectorIdxConstant(NumSubElts, DL)); in performInsertSubvectorCombine()
21290 int NumSubElts = NumElts / 4; in isLoadOrMultipleLoads() local
21291 for (int I = 0; I < NumSubElts; I++) { in isLoadOrMultipleLoads()
21294 SV1->getMaskElt(I + NumSubElts) != I + NumSubElts || in isLoadOrMultipleLoads()
21295 SV1->getMaskElt(I + NumSubElts * 2) != I + NumSubElts * 2 || in isLoadOrMultipleLoads()
21296 SV1->getMaskElt(I + NumSubElts * 3) != I + NumElts) in isLoadOrMultipleLoads()
21300 SV2->getMaskElt(I + NumSubElts) != I + NumSubElts || in isLoadOrMultipleLoads()
21301 SV2->getMaskElt(I + NumSubElts * 2) != I + NumElts) in isLoadOrMultipleLoads()
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| H A D | AArch64TargetTransformInfo.cpp | 5823 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
5824 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4998 int NumSubElts, Index; in lowerVECTOR_SHUFFLEAsVSlideup() local
4999 if (!ShuffleVectorInst::isInsertSubvectorMask(Mask, NumElts, NumSubElts, in lowerVECTOR_SHUFFLEAsVSlideup()
5016 if (NumSubElts + Index >= (int)NumElts) in lowerVECTOR_SHUFFLEAsVSlideup()
5021 SDValue VL = DAG.getConstant(NumSubElts + Index, DL, XLenVT); in lowerVECTOR_SHUFFLEAsVSlideup()
5358 unsigned NumSubElts; in isLegalBitRotate() local
5360 NumElts, NumSubElts, RotateAmt)) in isLegalBitRotate()
5362 RotateVT = MVT::getVectorVT(MVT::getIntegerVT(EltSizeInBits * NumSubElts), in isLegalBitRotate()
5363 NumElts / NumSubElts); in isLegalBitRotate()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 5728 int NumSubElts; local
5730 Mask, NumSrcElts, NumSubElts, Index)) {
5731 if (Index + NumSubElts > NumSrcElts &&
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 15747 unsigned NumSubElts = SubVT.getVectorNumElements(); in PerformInsertSubvectorCombine() local
15749 (IdxVal != 0 && IdxVal != NumSubElts)) in PerformInsertSubvectorCombine()
15760 DCI.DAG.getVectorIdxConstant(NumSubElts, DL)); in PerformInsertSubvectorCombine()
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