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Searched refs:NumPredsLeft (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGVLIW.cpp107 /// releaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
113 if (SuccSU->NumPredsLeft == 0) { in releaseSucc()
122 --SuccSU->NumPredsLeft; in releaseSucc()
128 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) { in releaseSucc()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAG.cpp150 assert(NumPredsLeft < std::numeric_limits<unsigned>::max() && in addPred()
152 ++NumPredsLeft; in addPred()
197 assert(NumPredsLeft > 0 && "NumPredsLeft will underflow!"); in removePred()
198 --NumPredsLeft; in removePred()
345 dbgs() << " # preds left : " << NumPredsLeft << "\n"; in dumpAttributes()
427 if (SUnit.NumPredsLeft != 0) { in VerifyScheduledDAG()
H A DPostRASchedulerList.cpp457 if (SuccSU->NumPredsLeft == 0) { in ReleaseSucc()
464 --SuccSU->NumPredsLeft; in ReleaseSucc()
479 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in ReleaseSucc()
533 if (!SUnit.NumPredsLeft && !SUnit.isAvailable) { in ListScheduleTopDown()
H A DMachineScheduler.cpp716 if (SuccSU->NumPredsLeft == 0) { in releaseSucc()
728 --SuccSU->NumPredsLeft; in releaseSucc()
729 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in releaseSucc()
924 if (!SU.NumPredsLeft) in findRootsAndBiasEdges()
3458 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft; in biasPhysReg()
H A DVLIWMachineScheduler.cpp549 if (SU->NumPredsLeft == 0) in isSingleUnscheduledPred()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCFGSort.cpp196 SmallVector<unsigned, 16> NumPredsLeft(MF.getNumBlockIDs(), 0); in sortBlocks() local
204 NumPredsLeft[MBB.getNumber()] = N; in sortBlocks()
250 if (--NumPredsLeft[Succ->getNumber()] == 0) { in sortBlocks()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp273 if (!SU->NumPredsLeft) in fastSchedule()
391 if (!SU->NumPredsLeft) in schedule()
412 SU->NumPredsLeft == 0); in schedule()
439 ++SuccSU->NumPredsLeft; in undoReleaseSucc()
450 if (SuccSU->NumPredsLeft == 0) { in releaseSucc()
458 --SuccSU->NumPredsLeft; in releaseSucc()
473 if (SuccSU->NumPredsLeft == 0 && InOrOutBlock) in releaseSuccessors()
480 assert (!SU->NumPredsLeft); in nodeScheduled()
1844 SUnits[i].NumPredsLeft = SUnitsLinksBackup[i].NumPredsLeft; in restoreSULinksLeft()
H A DGCNMinRegStrategy.cpp83 NumPreds[I] = SUnits[I].NumPredsLeft; in initNumPreds()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHazardRecognizer.cpp150 S.getSUnit()->NumPredsLeft == 1) { in EmitInstruction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h274 unsigned NumPredsLeft = 0; ///< # of preds not scheduled. variable
465 return NumPredsLeft == 0; in isTopReady()