| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86ShuffleDecode.cpp | 150 unsigned NumLanes = Size / 128; in DecodePSHUFMask() local
151 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask()
152 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSHUFMask()
221 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKHMask() local
222 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodeUNPCKHMask()
223 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKHMask()
237 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKLMask() local
238 if (NumLanes == 0 ) NumLanes = 1; // Handle MMX in DecodeUNPCKLMask()
239 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKLMask()
267 unsigned NumLanes = NumElts / NumElementsInLane; in decodeVSHUF64x2FamilyMask() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 415 unsigned NumLanes = Size / 4; in allocateSGPRSpillToVGPRLane() local
417 if (NumLanes > WaveSize) in allocateSGPRSpillToVGPRLane()
427 for (unsigned I = 0; I < NumLanes; ++I, ++NumSpillLanes) { in allocateSGPRSpillToVGPRLane()
462 unsigned NumLanes = Size / 4; in allocateVGPRSpillToAGPR() local
463 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
491 for (int I = NumLanes - 1; I >= 0; --I) { in allocateVGPRSpillToAGPR()
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| H A D | AMDGPURegisterBankInfo.cpp | 1963 unsigned NumLanes = DstRegs.size(); in foldExtractEltToCmpSelect() local
1964 if (!NumLanes) in foldExtractEltToCmpSelect()
1965 NumLanes = 1; in foldExtractEltToCmpSelect()
1970 SmallVector<Register, 2> Res(NumLanes); in foldExtractEltToCmpSelect()
1971 for (unsigned L = 0; L < NumLanes; ++L) in foldExtractEltToCmpSelect()
1980 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
1982 UnmergeToEltTy.getReg(I * NumLanes + L), Res[L]); in foldExtractEltToCmpSelect()
1991 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
1992 Register DstReg = (NumLanes == 1) ? MI.getOperand(0).getReg() : DstRegs[L]; in foldExtractEltToCmpSelect()
2064 unsigned NumLanes = InsRegs.size(); in foldInsertEltToCmpSelect() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 477 unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1); in DecodePALIGNRMask() local
478 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask()
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| H A D | X86InstCombineIntrinsic.cpp | 450 unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128; in simplifyX86pack() local
455 unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; in simplifyX86pack()
493 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack()
3305 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128; in simplifyDemandedVectorEltsIntrinsic() local
3306 unsigned VWidthPerLane = VWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
3307 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
3315 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
3330 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
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| H A D | X86ISelLowering.cpp | 5168 unsigned NumLanes = VT.getSizeInBits() / 128; in createPackShuffleMask() local
5175 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in createPackShuffleMask()
5188 int NumLanes = VT.getSizeInBits() / 128; in getPackDemandedElts() local
5191 int NumEltsPerLane = NumElts / NumLanes; in getPackDemandedElts()
5192 int NumInnerEltsPerLane = NumInnerElts / NumLanes; in getPackDemandedElts()
5198 for (int Lane = 0; Lane != NumLanes; ++Lane) { in getPackDemandedElts()
9437 int NumLanes = NumElts / NumEltsPerLane; in isMultiLaneShuffleMask() local
9438 if (NumLanes > 1) { in isMultiLaneShuffleMask()
9439 for (int i = 0; i != NumLanes; ++i) { in isMultiLaneShuffleMask()
9596 int NumLanes = VT.getSizeInBits() / 128; in IsElementEquivalent() local
[all …]
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| /freebsd/sys/dev/mpi3mr/mpi/ |
| H A D | mpi30_tool.h | 206 U8 NumLanes; /* 0x11 */ member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.h | 169 template <unsigned NumLanes, char LaneKind>
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| H A D | AArch64InstPrinter.cpp | 1739 template <unsigned NumLanes, char LaneKind>
1748 if (NumLanes) in printMatrixIndex()
1749 Suffix += itostr(NumLanes) + LaneKind; in printMatrixIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 575 int NumLanes = VectorBitWidth / 128; in getHorizDemandedEltsForFirstOperand() local
577 int NumEltsPerLane = NumElts / NumLanes; in getHorizDemandedEltsForFirstOperand()
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| /freebsd/contrib/llvm-project/clang/utils/TableGen/ |
| H A D | NeonEmitter.cpp | 769 unsigned NumLanes; in fromTypedefName() local
770 Name.substr(0, I).getAsInteger(10, NumLanes); in fromTypedefName()
772 T.Bitwidth = T.ElementBitwidth * NumLanes; in fromTypedefName()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 1404 int NumLanes; // Total number of lanes (aka vectorization factor). member in llvm::slpvectorizer::BoUpSLP::LookAheadHeuristics
1409 ScalarEvolution &SE, const BoUpSLP &R, int NumLanes, in LookAheadHeuristics() argument
1411 : TLI(TLI), DL(DL), SE(SE), R(R), NumLanes(NumLanes), in LookAheadHeuristics()
1482 ElementCount::getFixed(NumLanes)) && in getShallowScore()
1483 ((int)V1->getNumUses() == NumLanes || in getShallowScore()
1511 getWidenedType(LI1->getType(), NumLanes), LI1->getAlign())) in getShallowScore()
1517 if (std::abs(*Dist) > NumLanes / 2) in getShallowScore()
1563 if (std::abs(Dist) > NumLanes / 2) in getShallowScore()
1777 for (unsigned Lane = 0, NumLanes in clearUsed() local
2142 unsigned NumLanes = VL.size(); appendOperandsOfVL() local
2284 unsigned NumLanes = getNumLanes(); reorder() local
3011 unsigned NumLanes = Scalars.size(); setOperandsInOrder() local
6024 unsigned NumLanes = TE->Scalars.size(); findExternalStoreUsersReorderIndices() local
[all...] |
| H A D | VPlanRecipes.cpp | 718 for (unsigned Lane = 0, NumLanes = State.VF.getKnownMinValue(); in execute() local
719 Lane != NumLanes; ++Lane) { in execute()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 2831 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; in upgradeX86IntrinsicCall() local
2833 unsigned ControlBitsMask = NumLanes - 1; in upgradeX86IntrinsicCall()
2834 unsigned NumControlBits = NumLanes / 2; in upgradeX86IntrinsicCall()
2837 for (unsigned l = 0; l != NumLanes; ++l) { in upgradeX86IntrinsicCall()
2840 if (l >= NumLanes / 2) in upgradeX86IntrinsicCall()
2841 LaneMask += NumLanes; in upgradeX86IntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2371 size_t NumLanes = Op.getSimpleValueType().getVectorNumElements(); in unrollVectorShift() local
2379 for (size_t i = 0; i < NumLanes; ++i) { in unrollVectorShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 740 class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass {
741 let Name = "MVEVectorIndex"#NumLanes;
743 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">";
746 class MVEVectorIndex<int NumLanes> : Operand<i32> {
748 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>;
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| H A D | ARMISelLowering.cpp | 16915 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local
16916 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVCVTCombine()
16935 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
17056 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVMulVCTPCombine() local
17057 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVMulVCTPCombine()
17086 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, ConvInput); in PerformVMulVCTPCombine()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 15260 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
15261 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
15286 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
15287 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
15390 unsigned NumLanes = Ty->getPrimitiveSizeInBits() == 512 ? 4 : 2; in EmitX86BuiltinExpr() local
15391 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
15395 unsigned Index = (Imm % NumLanes) * NumLaneElts; in EmitX86BuiltinExpr()
15396 Imm /= NumLanes; // Discard the bits we just used. in EmitX86BuiltinExpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2260 template <unsigned NumLanes>
2263 return VectorIndex.Val < NumLanes; in isVectorIndexInRange()
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