| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86ShuffleDecode.cpp | 151 unsigned NumLanes = Size / 128; in DecodePSHUFMask() local
152 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask()
153 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSHUFMask()
222 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKHMask() local
223 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodeUNPCKHMask()
224 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKHMask()
238 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKLMask() local
239 if (NumLanes == 0 ) NumLanes = 1; // Handle MMX in DecodeUNPCKLMask()
240 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKLMask()
268 unsigned NumLanes = NumElts / NumElementsInLane; in decodeVSHUF64x2FamilyMask() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 447 unsigned NumLanes = Size / 4; in allocateSGPRSpillToVGPRLane() local
449 if (NumLanes > WaveSize) in allocateSGPRSpillToVGPRLane()
459 for (unsigned I = 0; I < NumLanes; ++I, ++NumSpillLanes) { in allocateSGPRSpillToVGPRLane()
494 unsigned NumLanes = Size / 4; in allocateVGPRSpillToAGPR() local
495 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
523 for (int I = NumLanes - 1; I >= 0; --I) { in allocateVGPRSpillToAGPR()
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| H A D | AMDGPURegisterBankInfo.cpp | 1991 unsigned NumLanes = DstRegs.size(); in foldExtractEltToCmpSelect() local
1992 if (!NumLanes) in foldExtractEltToCmpSelect()
1993 NumLanes = 1; in foldExtractEltToCmpSelect()
1998 SmallVector<Register, 2> Res(NumLanes); in foldExtractEltToCmpSelect()
1999 for (unsigned L = 0; L < NumLanes; ++L) in foldExtractEltToCmpSelect()
2008 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
2010 UnmergeToEltTy.getReg(I * NumLanes + L), Res[L]); in foldExtractEltToCmpSelect()
2019 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
2020 Register DstReg = (NumLanes == 1) ? MI.getOperand(0).getReg() : DstRegs[L]; in foldExtractEltToCmpSelect()
2092 unsigned NumLanes = InsRegs.size(); in foldInsertEltToCmpSelect() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 474 unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1); in DecodePALIGNRMask() local
475 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask()
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| H A D | X86InstCombineIntrinsic.cpp | 444 unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128; in simplifyX86pack() local
449 unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; in simplifyX86pack()
487 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack()
3337 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128; in simplifyDemandedVectorEltsIntrinsic() local
3338 unsigned VWidthPerLane = VWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
3339 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
3347 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
3362 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
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| H A D | X86ISelLowering.cpp | 5463 unsigned NumLanes = VT.getSizeInBits() / 128; in createPackShuffleMask() local
5470 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in createPackShuffleMask()
5483 int NumLanes = VT.getSizeInBits() / 128; in getPackDemandedElts() local
5486 int NumEltsPerLane = NumElts / NumLanes; in getPackDemandedElts()
5487 int NumInnerEltsPerLane = NumInnerElts / NumLanes; in getPackDemandedElts()
5493 for (int Lane = 0; Lane != NumLanes; ++Lane) { in getPackDemandedElts()
9873 int NumLanes = VT.getSizeInBits() / 128; in IsElementEquivalent() local
9874 int NumEltsPerLane = NumElts / NumLanes; in IsElementEquivalent()
9939 int NumLanes = NumElts / NumEltsPerLane; in isMultiLaneShuffleMask() local
9940 if (NumLanes > 1) { in isMultiLaneShuffleMask()
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| H A D | X86TargetTransformInfo.cpp | 1585 unsigned NumLanes = SrcTy->getPrimitiveSizeInBits() / 128; in getShuffleCost() local
1586 unsigned NumEltsPerLane = Mask.size() / NumLanes; in getShuffleCost()
1587 if ((Mask.size() % NumLanes) == 0) { in getShuffleCost()
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| /freebsd/sys/dev/mpi3mr/mpi/ |
| H A D | mpi30_tool.h | 209 U8 NumLanes; /* 0x11 */ member
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | X86.cpp | 1635 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
1636 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
1661 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
1662 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
1765 unsigned NumLanes = Ty->getPrimitiveSizeInBits() == 512 ? 4 : 2; in EmitX86BuiltinExpr() local
1766 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
1770 unsigned Index = (Imm % NumLanes) * NumLaneElts; in EmitX86BuiltinExpr()
1771 Imm /= NumLanes; // Discard the bits we just used. in EmitX86BuiltinExpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.h | 170 template <unsigned NumLanes, char LaneKind>
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| H A D | AArch64InstPrinter.cpp | 1752 template <unsigned NumLanes, char LaneKind>
1761 if (NumLanes) in printTypedVectorList()
1762 Suffix += itostr(NumLanes) + LaneKind; in printTypedVectorList()
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| /freebsd/contrib/llvm-project/clang/utils/TableGen/ |
| H A D | NeonEmitter.cpp | 817 unsigned NumLanes; in fromTypedefName() local
818 Name.substr(0, I).getAsInteger(10, NumLanes); in fromTypedefName()
820 T.Bitwidth = T.ElementBitwidth * NumLanes; in fromTypedefName()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 792 int NumLanes = VectorBitWidth / 128; in getHorizDemandedEltsForFirstOperand() local
794 int NumEltsPerLane = NumElts / NumLanes; in getHorizDemandedEltsForFirstOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 3122 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; in upgradeX86IntrinsicCall() local
3124 unsigned ControlBitsMask = NumLanes - 1; in upgradeX86IntrinsicCall()
3125 unsigned NumControlBits = NumLanes / 2; in upgradeX86IntrinsicCall()
3128 for (unsigned l = 0; l != NumLanes; ++l) { in upgradeX86IntrinsicCall()
3131 if (l >= NumLanes / 2) in upgradeX86IntrinsicCall()
3132 LaneMask += NumLanes; in upgradeX86IntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 2136 int NumLanes; // Total number of lanes (aka vectorization factor). member in llvm::slpvectorizer::BoUpSLP::LookAheadHeuristics
2141 ScalarEvolution &SE, const BoUpSLP &R, int NumLanes, in LookAheadHeuristics() argument
2143 : TLI(TLI), DL(DL), SE(SE), R(R), NumLanes(NumLanes), in LookAheadHeuristics()
2214 ElementCount::getFixed(NumLanes)) && in getShallowScore()
2215 ((int)V1->getNumUses() == NumLanes || in getShallowScore()
2247 getWidenedType(LI1->getType(), NumLanes), LI1->getAlign())) in getShallowScore()
2253 if (std::abs(*Dist) > NumLanes / 2) in getShallowScore()
2299 if (std::abs(Dist) > NumLanes / 2) in getShallowScore()
2520 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes; in clearUsed() local
2898 unsigned NumLanes = VL.size(); in appendOperands() local
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| H A D | VPlanRecipes.cpp | 1009 for (unsigned Lane = 0, NumLanes = State.VF.getFixedValue(); in execute() local
1010 Lane != NumLanes; ++Lane) { in execute()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2779 size_t NumLanes = Op.getSimpleValueType().getVectorNumElements(); in unrollVectorShift() local
2787 for (size_t i = 0; i < NumLanes; ++i) { in unrollVectorShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 760 class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass {
761 let Name = "MVEVectorIndex"#NumLanes;
763 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">";
766 class MVEVectorIndex<int NumLanes> : Operand<i32> {
768 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>;
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| H A D | ARMISelLowering.cpp | 16988 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local
16989 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVCVTCombine()
17008 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
17129 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVMulVCTPCombine() local
17130 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVMulVCTPCombine()
17159 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, ConvInput); in PerformVMulVCTPCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2261 template <unsigned NumLanes>
2264 return VectorIndex.Val < NumLanes; in isVectorIndexInRange()
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