Searched refs:NextVT (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4704 EVT NextVT; in CollectOpsToWiden()
4707 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); in CollectOpsToWiden()
4708 } while (!TLI.isTypeLegal(NextVT)); in CollectOpsToWiden()
4711 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT in CollectOpsToWiden()
4712 SDValue VecOp = DAG.getUNDEF(NextVT); in CollectOpsToWiden()
4715 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in CollectOpsToWiden()
4721 // Vector type, create a CONCAT_VECTORS of type NextVT in CollectOpsToWiden()
4733 NextVT, SubConcatOps); in CollectOpsToWiden()
4700 EVT NextVT; CollectOpsToWiden() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28003 MVT NextVT = MVT::getVectorVT(NextSVT, CurrNumElts / 2); in LowerVectorCTLZInRegLUT() local
28004 SDValue Shift = DAG.getConstant(CurrScalarSizeInBits, DL, NextVT); in LowerVectorCTLZInRegLUT()
28016 HiZ = DAG.getBitcast(NextVT, HiZ); in LowerVectorCTLZInRegLUT()
28021 SDValue ResNext = Res = DAG.getBitcast(NextVT, Res); in LowerVectorCTLZInRegLUT()
28022 SDValue R0 = DAG.getNode(ISD::SRL, DL, NextVT, ResNext, Shift); in LowerVectorCTLZInRegLUT()
28023 SDValue R1 = DAG.getNode(ISD::SRL, DL, NextVT, HiZ, Shift); in LowerVectorCTLZInRegLUT()
28024 R1 = DAG.getNode(ISD::AND, DL, NextVT, ResNext, R1); in LowerVectorCTLZInRegLUT()
28025 Res = DAG.getNode(ISD::ADD, DL, NextVT, R0, R1); in LowerVectorCTLZInRegLUT()
28026 CurrVT = NextVT; in LowerVectorCTLZInRegLUT()
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