Searched refs:NextVT (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 5083 EVT NextVT; in CollectOpsToWiden() local
5086 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); in CollectOpsToWiden()
5087 } while (!TLI.isTypeLegal(NextVT)); in CollectOpsToWiden()
5091 SDValue VecOp = DAG.getUNDEF(NextVT); in CollectOpsToWiden()
5110 NextVT, SubConcatOps); in CollectOpsToWiden()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28985 MVT NextVT = MVT::getVectorVT(NextSVT, CurrNumElts / 2); in LowerVectorCTLZInRegLUT() local
28986 SDValue Shift = DAG.getConstant(CurrScalarSizeInBits, DL, NextVT); in LowerVectorCTLZInRegLUT()
28998 HiZ = DAG.getBitcast(NextVT, HiZ); in LowerVectorCTLZInRegLUT()
29003 SDValue ResNext = Res = DAG.getBitcast(NextVT, Res); in LowerVectorCTLZInRegLUT()
29004 SDValue R0 = DAG.getNode(ISD::SRL, DL, NextVT, ResNext, Shift); in LowerVectorCTLZInRegLUT()
29005 SDValue R1 = DAG.getNode(ISD::SRL, DL, NextVT, HiZ, Shift); in LowerVectorCTLZInRegLUT()
29006 R1 = DAG.getNode(ISD::AND, DL, NextVT, ResNext, R1); in LowerVectorCTLZInRegLUT()
29007 Res = DAG.getNode(ISD::ADD, DL, NextVT, R0, R1); in LowerVectorCTLZInRegLUT()
29008 CurrVT = NextVT; in LowerVectorCTLZInRegLUT()
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