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Searched refs:NextReg (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp1789 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
1794 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1800 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1803 NextReg += 4; in emitAlignedDPRCS2Spills()
1809 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1813 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1819 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1822 NextReg += 4; in emitAlignedDPRCS2Spills()
1828 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1836 NextReg += 2; in emitAlignedDPRCS2Spills()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVAsmPrinter.cpp543 unsigned NextReg = RISCV::X28; in LowerKCFI_CHECK() local
550 while (!isRegAvailable(NextReg)) in LowerKCFI_CHECK()
551 ++NextReg; in LowerKCFI_CHECK()
552 Reg = NextReg++; in LowerKCFI_CHECK()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp1470 unsigned NextReg = SrcReg; in getSrcVReg() local
1473 NextReg = getIncomingRegForBlock(Inst, BB1); in getSrcVReg()
1478 NextReg = Inst->getOperand(1).getReg(); in getSrcVReg()
1479 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) in getSrcVReg()
1481 SrcReg = NextReg; in getSrcVReg()
H A DPPCISelLowering.cpp6892 unsigned NextReg = State.getFirstUnallocated(GPRs); in CC_AIX() local
6893 while (NextReg != GPRs.size() && in CC_AIX()
6894 !isGPRShadowAligned(GPRs[NextReg], ObjAlign)) { in CC_AIX()
6901 NextReg = State.getFirstUnallocated(GPRs); in CC_AIX()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp3010 Register NextReg = CSI[i + RegInc].getReg(); in computeCalleeSaveRegisterPairs() local
3014 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
3015 !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows, in computeCalleeSaveRegisterPairs()
3018 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
3021 if (AArch64::FPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
3022 !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI, in computeCalleeSaveRegisterPairs()
3024 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
3027 if (AArch64::FPR128RegClass.contains(NextReg)) in computeCalleeSaveRegisterPairs()
3028 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
3034 if (((RPI.Reg1 - AArch64::Z0) & 1) == 0 && (NextReg == RPI.Reg1 + 1)) in computeCalleeSaveRegisterPairs()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1476 Register NextReg = MI->getOperand(1).getReg(); in getTestBitReg() local
1478 if (!NextReg.isValid() || !MRI.hasOneNonDBGUse(NextReg)) in getTestBitReg()
1482 Reg = NextReg; in getTestBitReg()
1530 Register NextReg; in getTestBitReg() local
1538 NextReg = TestReg; in getTestBitReg()
1544 NextReg = TestReg; in getTestBitReg()
1551 NextReg = TestReg; in getTestBitReg()
1559 NextReg = TestReg; in getTestBitReg()
1574 NextReg = TestReg; in getTestBitReg()
1579 if (!NextReg.isValid()) in getTestBitReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2976 unsigned NextReg, NextRegNum, NextRegWidth; in ParseRegList() local
2979 if (!ParseAMDGPURegister(NextRegKind, NextReg, in ParseRegList()
2992 if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc)) in ParseRegList()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp6214 int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); in ConvertXWPOperands() local
6215 Inst.addOperand(MCOperand::createReg(NextReg)); in ConvertXWPOperands()