| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 229 SDValue NewVec = DAG.getNode( in ExpandRes_EXTRACT_VECTOR_ELT() local
237 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
241 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
394 SDValue NewVec = DAG.getBuildVector(NewVecVT, dl, NewElts); in ExpandOp_BUILD_VECTOR() local
397 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_BUILD_VECTOR()
422 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, in ExpandOp_INSERT_VECTOR_ELT() local
432 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
436 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, H in ExpandOp_INSERT_VECTOR_ELT()
[all...] |
| H A D | LegalizeDAG.cpp | 5663 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps); in PromoteNode() local
5664 Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec)); in PromoteNode()
5702 SDValue NewVec = CastVec; in PromoteNode() local
5710 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT, in PromoteNode()
5711 NewVec, Elt, InEltIdx); in PromoteNode()
5714 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec)); in PromoteNode()
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| H A D | LegalizeVectorTypes.cpp | 5427 SDValue NewVec; in WidenVecRes_BITCAST()
5438 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops); in WidenVecRes_BITCAST()
5445 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops); in WidenVecRes_BITCAST()
5448 NewVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewInVT, InOp); in WidenVecRes_BITCAST()
5450 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); in WidenVecRes_BITCAST()
5423 SDValue NewVec; WidenVecRes_BITCAST() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVRegularizer.cpp | 241 Value *NewVec = new ShuffleVectorInst(Inst, PVal, ConstVec, "", CI); in visitCallScalToVec() local
242 CI->setOperand(1, NewVec); in visitCallScalToVec()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3273 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); in bitcastExtractVectorElt() local
3274 MIRBuilder.buildBitcast(Dst, NewVec); in bitcastExtractVectorElt()
5671 auto NewVec = MIRBuilder.buildPadVectorWithUndefElements(MoreTy, MO); in moreElementsVector() local
5679 NewVec = MIRBuilder.buildInsertVectorElement(MoreTy, NewVec, in moreElementsVector()
5684 MO.setReg(NewVec.getReg(0)); in moreElementsVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8758 SDValue NewVec = DAG.getNode(ARMISD::BUILD_VECTOR, dl, MVT::v4f32, Parts); in LowerVECTOR_SHUFFLEUsingMovs() local
8759 return DAG.getBitcast(VT, NewVec); in LowerVECTOR_SHUFFLEUsingMovs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 51254 SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); in combineLoad() local
51255 return DCI.CombineTo(N, NewVec, TF, true); in combineLoad()
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