Home
last modified time | relevance | path

Searched refs:NewOpcode (Results 1 – 25 of 49) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp74 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
77 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
80 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
83 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
86 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
92 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
H A DHexagonGenMemAbsolute.cpp58 static bool isValidIndexedLoad(int &Opcode, int &NewOpcode);
59 static bool isValidIndexedStore(int &Opcode, int &NewOpcode);
H A DHexagonVLIWPacketizer.cpp453 int NewOpcode; in promoteToDotNew() local
455 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
457 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
458 MI.setDesc(HII->get(NewOpcode)); in promoteToDotNew()
463 int NewOpcode = HII->getDotOldOp(MI); in demoteToDotOld() local
464 MI.setDesc(HII->get(NewOpcode)); in demoteToDotOld()
882 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) : in canPromoteToDotNew() local
884 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp396 unsigned NewOpcode = AMDGPU::getMIMGOpcode(Info->BaseOpcode, NewEncoding, in shrinkMIMG() local
398 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
431 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; in shrinkMadFma() local
448 NewOpcode = AMDGPU::V_MADAK_F32; in shrinkMadFma()
451 NewOpcode = AMDGPU::V_FMAAK_F32; in shrinkMadFma()
454 NewOpcode = AMDGPU::V_MADAK_F16; in shrinkMadFma()
458 NewOpcode = AMDGPU::V_FMAAK_F16; in shrinkMadFma()
461 NewOpcode = AMDGPU::V_FMAAK_F16_t16; in shrinkMadFma()
464 NewOpcode = AMDGPU::V_FMAAK_F16_fake16; in shrinkMadFma()
468 NewOpcode = AMDGPU::V_FMAAK_F64; in shrinkMadFma()
[all …]
H A DR600MachineCFGStructurizer.cpp191 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
193 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
195 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
196 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
199 MachineBasicBlock::iterator I, int NewOpcode,
426 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
428 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
435 int NewOpcode, in insertInstrBefore() argument
438 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
448 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
[all …]
H A DAMDGPUPostLegalizerCombiner.cpp114 bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
407 auto [LoadMI, NewOpcode] = MatchData; in applyCombineSignExtendInReg()
408 LoadMI->setDesc(TII.get(NewOpcode)); in applyCombineSignExtendInReg()
418 MachineInstr &MI, unsigned &NewOpcode) const { in matchCombine_s_mul_u64()
426 NewOpcode = AMDGPU::G_AMDGPU_S_MUL_U64_U32; in matchCombine_s_mul_u64()
432 NewOpcode = AMDGPU::G_AMDGPU_S_MUL_I64_I32; in matchCombine_s_mul_u64()
H A DGCNCreateVOPD.cpp64 int NewOpcode = AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1, CI.IsVOPD3), in doReplace() local
67 assert(NewOpcode != -1 && in doReplace()
71 FirstMI->getDebugLoc(), SII->get(NewOpcode)) in doReplace()
H A DSIWholeQuadMode.cpp765 unsigned NewOpcode = 0; in splitBlock() local
768 NewOpcode = AMDGPU::S_AND_B32_term; in splitBlock()
771 NewOpcode = AMDGPU::S_AND_B64_term; in splitBlock()
774 NewOpcode = AMDGPU::S_MOV_B32_term; in splitBlock()
777 NewOpcode = AMDGPU::S_MOV_B64_term; in splitBlock()
780 NewOpcode = AMDGPU::S_ANDN2_B32_term; in splitBlock()
783 NewOpcode = AMDGPU::S_ANDN2_B64_term; in splitBlock()
791 TermMI->setDesc(TII->get(NewOpcode)); in splitBlock()
H A DSIOptimizeExecMasking.cpp597 const int NewOpcode = AMDGPU::getVCMPXOpFromVCMP(VCmp.getOpcode()); in optimizeVCMPSaveExecSequence() local
599 if (NewOpcode == -1) in optimizeVCMPSaveExecSequence()
619 VCmp.getDebugLoc(), TII->get(NewOpcode)); in optimizeVCMPSaveExecSequence()
H A DSIInstrInfo.cpp2609 unsigned NewOpcode = -1; in reMaterialize() local
2611 NewOpcode = AMDGPU::S_LOAD_DWORDX8_IMM; in reMaterialize()
2613 NewOpcode = AMDGPU::S_LOAD_DWORDX4_IMM; in reMaterialize()
2617 const MCInstrDesc &TID = get(NewOpcode); in reMaterialize()
7352 unsigned NewOpcode = getVALUOp(Inst); in moveToVALUImpl() local
7458 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; in moveToVALUImpl()
7464 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; in moveToVALUImpl()
7470 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; in moveToVALUImpl()
7476 NewOpcode = ST.getGeneration() >= AMDGPUSubtarget::GFX12 in moveToVALUImpl()
7484 NewOpcode = AMDGPU::V_ASHRREV_I64_e64; in moveToVALUImpl()
[all …]
H A DSIISelLowering.h79 unsigned NewOpcode) const;
81 unsigned NewOpcode) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp63 unsigned &NewOpcode) { in findVCMPToFoldIntoVPST() argument
78 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode()); in findVCMPToFoldIntoVPST()
79 if (NewOpcode == 0) in findVCMPToFoldIntoVPST()
271 unsigned NewOpcode; in InsertVPTBlocks() local
273 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) { in InsertVPTBlocks()
275 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode)); in InsertVPTBlocks()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp133 int NewOpcode; in InsertSPImmInst() local
135 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
136 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
141 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
142 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
148 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
149 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp523 unsigned NewOpcode = AluI->getOpcode(); in optLEAALU() local
524 NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
529 NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
587 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
593 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
598 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
611 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
615 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
618 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
622 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
263 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
264 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
266 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
451 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
469 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp198 int NewOpcode = -1; in encodeInstruction() local
201 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
202 if (NewOpcode == -1) in encodeInstruction()
203 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
206 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
209 if (NewOpcode == -1) in encodeInstruction()
210 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
212 if (NewOpcode != -1) { in encodeInstruction()
216 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp225 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex() local
230 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode), in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1576 std::string NewOpcode; in parseInstruction() local
1578 NewOpcode = std::string(Name); in parseInstruction()
1579 NewOpcode += '+'; in parseInstruction()
1580 Name = NewOpcode; in parseInstruction()
1583 NewOpcode = std::string(Name); in parseInstruction()
1584 NewOpcode += '-'; in parseInstruction()
1585 Name = NewOpcode; in parseInstruction()
1591 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in parseInstruction()
1599 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in parseInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp71 unsigned NewOpcode) const { in splitMove()
97 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
98 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
145 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
146 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
147 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
1121 unsigned NewOpcode; in convertToThreeAddress() local
1123 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
1126 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
1128 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
H A DSystemZFrameLowering.cpp747 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
751 if (!NewOpcode) { in emitEpilogue()
756 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
757 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
760 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
H A DSystemZInstrInfo.h189 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp1845 unsigned NewOpcode = 0u; in eliminateFrameIndex() local
1893 NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex()
1894 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
1913 if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) { in eliminateFrameIndex()
1919 MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ)); in eliminateFrameIndex()
H A DPPCISelDAGToDAG.cpp7418 unsigned NewOpcode; in PeepholePPC64ZExt() local
7422 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; in PeepholePPC64ZExt()
7423 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
7424 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
7425 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
7426 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
7427 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
7428 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
7429 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; in PeepholePPC64ZExt()
7430 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break; in PeepholePPC64ZExt()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp558 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch() local
559 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); in replaceWithCompactBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp563 int NewOpcode; in expand_DestructiveOp() local
565 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1) in expand_DestructiveOp()
566 Opcode = NewOpcode; in expand_DestructiveOp()
568 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1) in expand_DestructiveOp()
569 Opcode = NewOpcode; in expand_DestructiveOp()

12