Searched refs:NewN1 (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 42222 SDValue NewN1 = SimplifyMultipleUseDemandedVectorElts(N1, DemandedRHS, in SimplifyDemandedVectorEltsForTargetNode() local
42224 if (NewN0 || NewN1) { in SimplifyDemandedVectorEltsForTargetNode()
42226 NewN1 = NewN1 ? NewN1 : N1; in SimplifyDemandedVectorEltsForTargetNode()
42228 TLO.DAG.getNode(Opc, SDLoc(Op), VT, NewN0, NewN1)); in SimplifyDemandedVectorEltsForTargetNode()
42259 SDValue NewN1 = SimplifyMultipleUseDemandedVectorElts(N1, DemandedRHS, in SimplifyDemandedVectorEltsForTargetNode() local
42261 if (NewN0 || NewN1) { in SimplifyDemandedVectorEltsForTargetNode()
42263 NewN1 = NewN1 ? NewN1 : N1; in SimplifyDemandedVectorEltsForTargetNode()
42265 TLO.DAG.getNode(Opc, SDLoc(Op), VT, NewN0, NewN1)); in SimplifyDemandedVectorEltsForTargetNode()
47583 SDValue NewN1 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N1); in reduceVMULWidth() local
47587 SDValue MulLo = DAG.getNode(ISD::MUL, DL, ReducedVT, NewN0, NewN1); in reduceVMULWidth()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 5058 SDValue NewN1 = CmpZero ? DAG.getConstant(0, dl, OpVT) : LoBits; in SimplifySetCC() local
5059 return DAG.getSetCC(dl, VT, NewN0, NewN1, Cond); in SimplifySetCC()
|
| H A D | DAGCombiner.cpp | 18267 if (SDValue NewN1 = rebuildSetCC(N1)) in visitBRCOND() local
18269 ChainHandle.getValue(), NewN1, N2); in visitBRCOND()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 13759 SDValue NewN1 = DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV.getOperand(0), in combineOrOfCZERO()
13761 SDValue NewOr = DAG.getNode(ISD::OR, DL, VT, NewN0, NewN1);
13756 SDValue NewN1 = DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV.getOperand(0), combineOrOfCZERO() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 14699 SDValue NewN1 = DAG.getLogicalNOT(DL, N1, VT); in PerformORCombine_i1() local
14700 SDValue And = DAG.getNode(ISD::AND, DL, VT, NewN0, NewN1); in PerformORCombine_i1()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18234 SDValue NewN1 = DAG.getNode(N->getOperand(1).getOpcode(), DL, HalfVT, N1); in performVectorExtCombine() local
18235 SDValue NewOp = DAG.getNode(N->getOpcode(), DL, HalfVT, NewN0, NewN1); in performVectorExtCombine()
|