| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankLegalizeHelper.cpp | 785 Register NewDst = MRI.createVirtualRegister(VccRB_S1); in applyMappingDst() local
786 Op.setReg(NewDst); in applyMappingDst()
788 B.buildInstr(AMDGPU::G_AMDGPU_COPY_SCC_VCC, {SgprRB_S32}, {NewDst}); in applyMappingDst()
819 Register NewDst = MRI.createVirtualRegister(SgprRB_S32); in applyMappingDst() local
820 Op.setReg(NewDst); in applyMappingDst()
821 B.buildTrunc(Reg, NewDst); in applyMappingDst()
990 Register NewDst = MRI.createVirtualRegister(SgprRB_S32); in applyMappingPHI() local
991 MI.getOperand(0).setReg(NewDst); in applyMappingPHI()
992 B.buildTrunc(Dst, NewDst); in applyMappingPHI()
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| H A D | SIFixSGPRCopies.cpp | 157 bool tryMoveVGPRConstToSGPR(MachineOperand &MO, Register NewDst,
679 Register NewDst = MRI->createVirtualRegister(DestRC); in run() local
687 if (!tryMoveVGPRConstToSGPR(MO, NewDst, BlockToInsertCopy, in run()
691 TII->get(AMDGPU::COPY), NewDst) in run()
693 MO.setReg(NewDst); in run()
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| H A D | SIInstrInfo.cpp | 7712 Register NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in moveToVALUImpl() local
7716 BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst) in moveToVALUImpl()
7726 BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst) in moveToVALUImpl()
7733 MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst); in moveToVALUImpl()
7734 addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist); in moveToVALUImpl()
7741 Register NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in moveToVALUImpl() local
7742 MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst) in moveToVALUImpl()
7749 MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst); in moveToVALUImpl()
7752 addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist); in moveToVALUImpl()
7759 Register NewDst = MRI.createVirtualRegister(ST.useRealTrue16Insts() in moveToVALUImpl() local
[all …]
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| H A D | SIISelLowering.cpp | 16224 unsigned NewDst = 0; // Final initialized value will be in here in AddMemOpInit() local
16234 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddMemOpInit()
16242 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewDst) in AddMemOpInit()
16247 PrevDst = NewDst; in AddMemOpInit()
16251 MI.addOperand(MachineOperand::CreateReg(NewDst, false, true)); in AddMemOpInit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1720 auto NewDst = MRI.createGenericVirtualRegister(NewDstTy); in legalizeIntrinsic() local
1723 MI.getOperand(0).setReg(NewDst); in legalizeIntrinsic()
1728 OldDst, NewDst); in legalizeIntrinsic()
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| H A D | AArch64InstructionSelector.cpp | 3096 Register NewDst = in select() local
3098 LdSt.getOperand(0).setReg(NewDst); in select()
3099 MRI.setRegBank(NewDst, RB); in select()
3104 .addUse(NewDst) in select()
5820 Register NewDst = MRI.createVirtualRegister(&AArch64::FPR128RegClass); in emitConstantVector() local
5821 NewOp->getOperand(0).setReg(NewDst); in emitConstantVector()
5822 return MIRBuilder.buildInstr(NegOpc, {Dst}, {NewDst}); in emitConstantVector()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenDAGPatterns.cpp | 4454 TreePatternNodePtr NewDst = P.getDstPattern().clone(); in ExpandHwModeBasedTypes() local
4455 if (!NewSrc->setDefaultMode(Mode) || !NewDst->setDefaultMode(Mode)) { in ExpandHwModeBasedTypes()
4460 std::move(NewSrc), std::move(NewDst), in ExpandHwModeBasedTypes()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3048 Register NewDst; in widenScalar() local
3065 NewDst = MIRBuilder.buildSMax(WideTy, MidReg, MinVal).getReg(0); in widenScalar()
3073 NewDst = MIRBuilder.buildUMin(WideTy, ExtReg, MaxVal).getReg(0); in widenScalar()
3075 MIRBuilder.buildTrunc(OldDst, NewDst); in widenScalar()
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